VPCMPUD

VPCMPUD compares 4, 8 or 16 pairs of unsigned doublewords and writes one bit per pair to a mask register. VPCMPD is its signed twin and holds the table of predicates and the rules of the write mask; VPCMPUQ shows how unsigned order makes a range test one compare. As an AVX-512F instruction it takes a broadcast doubleword as its second source, which the byte and word forms cannot. SSE4.1 had only PMINUD and PMAXUD to build such a test.

Recorded on Zen 5#

• Unsigned order. In vpcmpud k3{k4}, zmm14, zmm8, 0x5, greater or equal, FFFFFFFFh against 1 and 80000000h against 1 set their bits, and 7FFFFFFFh against FFFFFFFFh did not: a signed compare would answer all three the other way.
• Bits 7:3 are ignored. vpcmpud k5, ymm1, ymm2, 0xf9 tested less than, setting the bits of 0 against 1 and of 1 against FFFFFFFFh, and gave 22h.
• Predicate 7 copies the mask. vpcmpud k3{k1}, zmm9, zmmword ptr [mem], 0x7 gave 32A0h, the low 16 bits of K1.

In compiled code#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 compile o[i] = a[i] < b[i] ? a[i] : 7 over uint32_t arrays to VPCMPUD with predicate 1, b[i] in memory, and a VPBLENDMD; GCC works on ZMM registers, Clang on YMM and prints the compare vpcmpltud. For _mm512_cmpgt_epu32_mask(x, _mm512_set1_epi32(*p)) Clang folds the broadcast, vpcmpnleud k0, zmm0, dword ptr [rdi]{1to16}, while GCC broadcasts with VPBROADCASTD first and compares registers with predicate 6.

AMD’s Zen 5 latency spreadsheet lists VPCMPUD as one macro-op on FP1 or FP2, two with a memory source, and 3, 4 and 6 cycles for XMM, YMM and ZMM.

In the optimization guide

What the optimization guide says about VPCMPUD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Zen 4

• Vectors and floating point: An AVX-512 compare that writes a mask register, such as VPCMPD, takes 3, 4 or 5 cycles for 128, 256 or 512 bits, where the older compares into a vector register take one cycle for integers and two for floats. sources differ

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    a = zmm2.d[i]
    b = src3.d[i]
    k1[i] = k2[i] and compare(imm8, a, b)
# imm8 & 7: 0 ==, 1 <, 2 <=, 3 false, 4 !=, 5 >=, 6 >, 7 true
# m32bcst: src3.d[i] is the m32 for every i
# the other bits of k1 are cleared

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPCMPUD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPBLENDMW
• VPBROADCASTB
• VPBROADCASTD
• VPBROADCASTMB2Q
• VPBROADCASTMW2D
• VPBROADCASTQ
• VPBROADCASTW
• VPCLMULQDQ
• VPCMPB
• VPCMPD
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW
• VPCMPGTB
• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPCMPQ
• VPCMPUB
• VPCMPUQ
• VPCMPUW
• VPCMPW
• VPCOMPRESSB
• VPCOMPRESSD
• VPCOMPRESSQ
• VPCOMPRESSW
• VPCONFLICTD
• VPCONFLICTQ
• VPDPBUSD
• VPDPBUSDS
• VPDPWSSD
• VPDPWSSDS
• VPERMB
• VPERMD
• VPERMI2B
• VPERMI2D
• VPERMI2PD
• VPERMI2PS
• VPERMI2Q

All 686 AVX10.1 instructions