VPCMPUW

VPCMPUW compares 8, 16 or 32 pairs of unsigned words and writes one bit per pair to a mask register. It is the word form of VPCMPUB, whose page shows how unsigned order turns a range test into one compare; VPCMPD lists the predicates, and VPCMPW is the signed twin. It needs AVX512BW (or AVX10.1) and has no broadcast form. Before AVX-512, an unsigned compare of words took a PMINUW or PMAXUW and an equality test, both from SSE4.1.

Recorded on Zen 5#

• Unsigned order. In vpcmpuw k3, ymm7, ymmword ptr [mem], 0x2, less or equal, 8000h against FFFFh set its bit and FFFFh against 1 left it clear, the other way round from a signed compare.
• Predicate 5 on one register. vpcmpuw k7, ymm9, ymm9, 0x5, greater or equal, set all 16 bits.
• Bits 7:3 are ignored. With 0xF9, less than, in vpcmpuw k6{k3}, zmm24, zmm3, 0xf9, 8000h against FFFFh and 0 against 8000h set their bits, and no bit outside K3 was set.

In compiled code#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 compile o[i] = a[i] < b[i] ? a[i] : 7 over uint16_t arrays to VPCMPUW with b[i] as memory operand, predicate 1 (Clang prints vpcmpltuw), and a VPBLENDMW with a vector of sevens, GCC on ZMM and Clang on YMM registers. For the range test (uint16_t)(a[i] - 100) <= 900 both add -100 with VPADDW and compare once: GCC with predicate 2 against 900, Clang with vpcmpltuw against 901.

AMD’s Zen 5 latency spreadsheet lists VPCMPUW as VPCMPW: one macro-op on FP1 or FP2, two with a memory source, and 3, 4 and 6 cycles for XMM, YMM and ZMM.

In the optimization guide

What the optimization guide says about VPCMPUW, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Zen 4

• Vectors and floating point: An AVX-512 compare that writes a mask register, such as VPCMPD, takes 3, 4 or 5 cycles for 128, 256 or 512 bits, where the older compares into a vector register take one cycle for integers and two for floats. sources differ

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    a = zmm2.w[i]
    b = src3.w[i]
    k1[i] = k2[i] and compare(imm8, a, b)
# imm8 & 7: 0 ==, 1 <, 2 <=, 3 false, 4 !=, 5 >=, 6 >, 7 true
# the other bits of k1 are cleared

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPCMPUW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPBROADCASTD
• VPBROADCASTMB2Q
• VPBROADCASTMW2D
• VPBROADCASTQ
• VPBROADCASTW
• VPCLMULQDQ
• VPCMPB
• VPCMPD
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW
• VPCMPGTB
• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPCMPQ
• VPCMPUB
• VPCMPUD
• VPCMPUQ
• VPCMPW
• VPCOMPRESSB
• VPCOMPRESSD
• VPCOMPRESSQ
• VPCOMPRESSW
• VPCONFLICTD
• VPCONFLICTQ
• VPDPBUSD
• VPDPBUSDS
• VPDPWSSD
• VPDPWSSDS
• VPERMB
• VPERMD
• VPERMI2B
• VPERMI2D
• VPERMI2PD
• VPERMI2PS
• VPERMI2Q
• VPERMI2W
• VPERMILPD

All 686 AVX10.1 instructions