VPCMPW

VPCMPW compares 8, 16 or 32 pairs of signed words and writes one bit per pair to a mask register. It is the word form of VPCMPB, whose page shows which compares GCC and Clang give to this opcode and which to the shorter VPCMPEQW and VPCMPGTW; VPCMPD lists the predicates of the immediate, and VPCMPUW is the unsigned twin. It needs AVX512BW (or AVX10.1) and has no broadcast form.

Recorded on Zen 5#

• Signed order. With predicate 5, greater or equal, in vpcmpw k1{k3}, zmm0, zmm31, 0x5, 7FFFh against FFFFh set its bit, 32767 not being below -1, and 8000h against FFFFh left it clear.
• Only bits 2:0 of the immediate. vpcmpw k6, ymm9, ymm9, 0xf9 tested less than, as 1 does, and gave 0 for 16 equal pairs.
• Masked elements read 0. vpcmpw k6{k7}, xmm17, xmm30, 0x0 set the bits of the four equal pairs among the five that K7 selected, giving A3h, and cleared bits 63:8.

In compiled code#

For o[i] = a[i] >= b[i] ? c[i] : 0 over int16_t arrays, GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 load a[i], compare it with b[i] in memory and load c[i] with a zero-masked VMOVDQU16: GCC with VPCMPW and predicate 5 on ZMM registers, Clang with the same predicate printed vpcmpnltw on YMM registers. With != both use predicate 4, which Clang prints vpcmpneqw. The SSE and AVX2 forms have no “not equal” or “greater or equal”: they need a compare and an inversion.

AMD’s Zen 5 latency spreadsheet lists VPCMPW as one macro-op on pipes FP1 or FP2, two with a memory source, with 3, 4 and 6 cycles of latency for XMM, YMM and ZMM, as VPCMPB.

In the optimization guide

What the optimization guide says about VPCMPW, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Zen 4

• Vectors and floating point: An AVX-512 compare that writes a mask register, such as VPCMPD, takes 3, 4 or 5 cycles for 128, 256 or 512 bits, where the older compares into a vector register take one cycle for integers and two for floats. sources differ

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    sa = zmm2.sw[i]
    sb = src3.sw[i]
    k1[i] = k2[i] and compare(imm8, sa, sb)
# imm8 & 7: 0 ==, 1 <, 2 <=, 3 false, 4 !=, 5 >=, 6 >, 7 true
# the other bits of k1 are cleared

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPCMPW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPBROADCASTMB2Q
• VPBROADCASTMW2D
• VPBROADCASTQ
• VPBROADCASTW
• VPCLMULQDQ
• VPCMPB
• VPCMPD
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW
• VPCMPGTB
• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPCMPQ
• VPCMPUB
• VPCMPUD
• VPCMPUQ
• VPCMPUW
• VPCOMPRESSB
• VPCOMPRESSD
• VPCOMPRESSQ
• VPCOMPRESSW
• VPCONFLICTD
• VPCONFLICTQ
• VPDPBUSD
• VPDPBUSDS
• VPDPWSSD
• VPDPWSSDS
• VPERMB
• VPERMD
• VPERMI2B
• VPERMI2D
• VPERMI2PD
• VPERMI2PS
• VPERMI2Q
• VPERMI2W
• VPERMILPD
• VPERMILPS

All 686 AVX10.1 instructions