x86-64.net

Instruction

VPCMPW

Compares packed signed words with a predicate chosen by an immediate and writes the results to a mask register.

Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VPCMPW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPCMPW k {k}, xmm, xmm, imm8 VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512EVEX.128.66.0F3A.W1 3F /r ibAVX10.1 or AVX512BW + AVX512VL
VPCMPW k {k}, xmm, m128, imm8 VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512EVEX.128.66.0F3A.W1 3F /r ibAVX10.1 or AVX512BW + AVX512VL
VPCMPW k {k}, ymm, ymm, imm8 VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512EVEX.256.66.0F3A.W1 3F /r ibAVX10.1 or AVX512BW + AVX512VL
VPCMPW k {k}, ymm, m256, imm8 VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512EVEX.256.66.0F3A.W1 3F /r ibAVX10.1 or AVX512BW + AVX512VL
VPCMPW k {k}, zmm, zmm, imm8 VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512EVEX.512.66.0F3A.W1 3F /r ibAVX10.1 or AVX512BW
VPCMPW k {k}, zmm, m512, imm8 VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512EVEX.512.66.0F3A.W1 3F /r ibAVX10.1 or AVX512BW

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPCMPW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_cmp_epi16_mask __mmask8 _mm_cmp_epi16_mask(__m128i a, __m128i b, const int p)

VPCMPW k, xmm, xmm, imm8 EVEX.128 -mavx512vl -mavx512bw

_mm_mask_cmp_epi16_mask __mmask8 _mm_mask_cmp_epi16_mask(__mmask8 m, __m128i a, __m128i b, const int p)

VPCMPW k, xmm, xmm, imm8 EVEX.128 -mavx512vl -mavx512bw

_mm_cmpge_epi16_mask __mmask8 _mm_cmpge_epi16_mask(__m128i A, __m128i B)

VPCMPW k, xmm, xmm, imm8 EVEX.128 -mavx512vl -mavx512bw

_mm_mask_cmpge_epi16_mask __mmask8 _mm_mask_cmpge_epi16_mask(__mmask8 k, __m128i A, __m128i B)

VPCMPW k, xmm, xmm, imm8 EVEX.128 -mavx512vl -mavx512bw

_mm_cmple_epi16_mask __mmask8 _mm_cmple_epi16_mask(__m128i A, __m128i B)

VPCMPW k, xmm, xmm, imm8 EVEX.128 -mavx512vl -mavx512bw

_mm_mask_cmple_epi16_mask __mmask8 _mm_mask_cmple_epi16_mask(__mmask8 k, __m128i A, __m128i B)

VPCMPW k, xmm, xmm, imm8 EVEX.128 -mavx512vl -mavx512bw

_mm_cmpneq_epi16_mask __mmask8 _mm_cmpneq_epi16_mask(__m128i A, __m128i B)

VPCMPW k, xmm, xmm, imm8 EVEX.128 -mavx512vl -mavx512bw

_mm_mask_cmpneq_epi16_mask __mmask8 _mm_mask_cmpneq_epi16_mask(__mmask8 k, __m128i A, __m128i B)

VPCMPW k, xmm, xmm, imm8 EVEX.128 -mavx512vl -mavx512bw

_mm_cmpneq_epu16_mask __mmask8 _mm_cmpneq_epu16_mask(__m128i A, __m128i B)

VPCMPW k, xmm, xmm, imm8 EVEX.128 -mavx512vl -mavx512bw

_mm_mask_cmpneq_epu16_mask __mmask8 _mm_mask_cmpneq_epu16_mask(__mmask8 k, __m128i A, __m128i B)

VPCMPW k, xmm, xmm, imm8 EVEX.128 -mavx512vl -mavx512bw

_mm256_cmp_epi16_mask __mmask16 _mm256_cmp_epi16_mask(__m256i a, __m256i b, const int p)

VPCMPW k, ymm, ymm, imm8 EVEX.256 -mavx512vl -mavx512bw

_mm256_mask_cmp_epi16_mask __mmask16 _mm256_mask_cmp_epi16_mask(__mmask16 m, __m256i a, __m256i b, const int p)

VPCMPW k, ymm, ymm, imm8 EVEX.256 -mavx512vl -mavx512bw

_mm256_cmpge_epi16_mask __mmask16 _mm256_cmpge_epi16_mask(__m256i A, __m256i B)

VPCMPW k, ymm, ymm, imm8 EVEX.256 -mavx512vl -mavx512bw

_mm256_mask_cmpge_epi16_mask __mmask16 _mm256_mask_cmpge_epi16_mask(__mmask16 k, __m256i A, __m256i B)

VPCMPW k, ymm, ymm, imm8 EVEX.256 -mavx512vl -mavx512bw

_mm256_cmple_epi16_mask __mmask16 _mm256_cmple_epi16_mask(__m256i A, __m256i B)

VPCMPW k, ymm, ymm, imm8 EVEX.256 -mavx512vl -mavx512bw

_mm256_mask_cmple_epi16_mask __mmask16 _mm256_mask_cmple_epi16_mask(__mmask16 k, __m256i A, __m256i B)

VPCMPW k, ymm, ymm, imm8 EVEX.256 -mavx512vl -mavx512bw

_mm256_cmpneq_epi16_mask __mmask16 _mm256_cmpneq_epi16_mask(__m256i A, __m256i B)

VPCMPW k, ymm, ymm, imm8 EVEX.256 -mavx512vl -mavx512bw

_mm256_mask_cmpneq_epi16_mask __mmask16 _mm256_mask_cmpneq_epi16_mask(__mmask16 k, __m256i A, __m256i B)

VPCMPW k, ymm, ymm, imm8 EVEX.256 -mavx512vl -mavx512bw

_mm256_cmpneq_epu16_mask __mmask16 _mm256_cmpneq_epu16_mask(__m256i A, __m256i B)

VPCMPW k, ymm, ymm, imm8 EVEX.256 -mavx512vl -mavx512bw

_mm256_mask_cmpneq_epu16_mask __mmask16 _mm256_mask_cmpneq_epu16_mask(__mmask16 k, __m256i A, __m256i B)

VPCMPW k, ymm, ymm, imm8 EVEX.256 -mavx512vl -mavx512bw

_mm512_cmp_epi16_mask __mmask32 _mm512_cmp_epi16_mask(__m512i a, __m512i b, const int p)

VPCMPW k, zmm, zmm, imm8 EVEX.512 -mavx512bw

_mm512_mask_cmp_epi16_mask __mmask32 _mm512_mask_cmp_epi16_mask(__mmask32 m, __m512i a, __m512i b, const int p)

VPCMPW k, zmm, zmm, imm8 EVEX.512 -mavx512bw

_mm512_cmpge_epi16_mask __mmask32 _mm512_cmpge_epi16_mask(__m512i A, __m512i B)

VPCMPW k, zmm, zmm, imm8 EVEX.512 -mavx512bw

_mm512_mask_cmpge_epi16_mask __mmask32 _mm512_mask_cmpge_epi16_mask(__mmask32 k, __m512i A, __m512i B)

VPCMPW k, zmm, zmm, imm8 EVEX.512 -mavx512bw

_mm512_cmple_epi16_mask __mmask32 _mm512_cmple_epi16_mask(__m512i A, __m512i B)

VPCMPW k, zmm, zmm, imm8 EVEX.512 -mavx512bw

_mm512_mask_cmple_epi16_mask __mmask32 _mm512_mask_cmple_epi16_mask(__mmask32 k, __m512i A, __m512i B)

VPCMPW k, zmm, zmm, imm8 EVEX.512 -mavx512bw

_mm512_cmpneq_epi16_mask __mmask32 _mm512_cmpneq_epi16_mask(__m512i A, __m512i B)

VPCMPW k, zmm, zmm, imm8 EVEX.512 -mavx512bw

_mm512_mask_cmpneq_epi16_mask __mmask32 _mm512_mask_cmpneq_epi16_mask(__mmask32 k, __m512i A, __m512i B)

VPCMPW k, zmm, zmm, imm8 EVEX.512 -mavx512bw

_mm512_cmpneq_epu16_mask __mmask32 _mm512_cmpneq_epu16_mask(__m512i A, __m512i B)

VPCMPW k, zmm, zmm, imm8 EVEX.512 -mavx512bw

_mm512_mask_cmpneq_epu16_mask __mmask32 _mm512_mask_cmpneq_epu16_mask(__mmask32 k, __m512i A, __m512i B)

VPCMPW k, zmm, zmm, imm8 EVEX.512 -mavx512bw

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512BW_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512BW_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512BW_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.