VPCOMPRESSB

VPCOMPRESSB packs the bytes that a mask selects into the low end of its destination, in their original order. It is the byte version of VPCOMPRESSD, whose page explains left-packing and how the register and memory destinations differ; AVX512_VBMI2 added it together with VPCOMPRESSW for words and the reverse operations, VPEXPANDB and VPEXPANDW. Before VBMI2, AVX-512 could compress only doublewords and quadwords, so packing bytes took several instructions per vector.

Filtering text#

Bytes are what text is made of, so the typical use is dropping characters from a string: compare 64 bytes against a space with VPCMPB into a mask register, compress the bytes whose bits are set, store them, and advance the output by the number kept. The mask has one bit per byte, all 64 bits of a mask register for a ZMM source, so it moves to a general-purpose register with KMOVQ and is counted with POPCNT on 64 bits.

Compilers leave this to the programmer. GCC 14 and Clang 23 at -O2 emit VPCOMPRESSB for the intrinsics _mm512_maskz_compress_epi8 and _mm512_mask_compressstoreu_epi8 once VBMI2 is enabled, with -mavx512vbmi2 or a -march such as icelake-server, znver4 or znver5 (x86-64-v4 does not include it). Neither vectorized the loop if (s[i] != ' ') d[j++] = s[i];, even at -O3 for znver5: both kept it scalar.

The memory form on Zen 5#

AMD’s Zen 5 guide lists the register form as two macro-ops with a latency of 2, 4 and 5 cycles for xmm, ymm and zmm, and the memory form, like every compress to memory, as microcoded. The register form followed by an ordinary store is the usual alternative: it writes a whole vector, so the output buffer needs room for one at its end, as the VPCOMPRESSD page explains, or the store can be a VMOVDQU8 under a mask of the low n bits, which BZHI of an all-ones value gives. The cases recorded on Zen 5 agree with the page’s pseudocode for both forms: the memory form left the bytes above the packed ones as they were, and the register form with {z} cleared them.

In the optimization guide

What the optimization guide says about VPCOMPRESSB, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Zen 4

• Vectors and floating point: VPCOMPRESSD and the other compress instructions are microcoded when they write to memory: compressing into a register and then storing it is faster.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

j = 0
for i in range(VL // 8):
    if k1[i]:
        mem.b[j] = zmm2.b[i]
        j += 1
# the memory above element j is not written

j = 0
for i in range(VL // 8):
    if k1[i]:
        zmm1.b[j] = zmm2.b[i]
        j += 1
if zeroing:
    for i in range(j, VL // 8):
        zmm1.b[i] = 0
# else: the elements from j up keep their values
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPCOMPRESSB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPBROADCASTMW2D
• VPBROADCASTQ
• VPBROADCASTW
• VPCLMULQDQ
• VPCMPB
• VPCMPD
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW
• VPCMPGTB
• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPCMPQ
• VPCMPUB
• VPCMPUD
• VPCMPUQ
• VPCMPUW
• VPCMPW
• VPCOMPRESSD
• VPCOMPRESSQ
• VPCOMPRESSW
• VPCONFLICTD
• VPCONFLICTQ
• VPDPBUSD
• VPDPBUSDS
• VPDPWSSD
• VPDPWSSDS
• VPERMB
• VPERMD
• VPERMI2B
• VPERMI2D
• VPERMI2PD
• VPERMI2PS
• VPERMI2Q
• VPERMI2W
• VPERMILPD
• VPERMILPS
• VPERMPD

All 686 AVX10.1 instructions