VPCOMPRESSD

VPCOMPRESSD keeps the doublewords that a mask selects and packs them together at the low end, in their original order: with mask bits 1, 2 and 5 set, elements 1, 2 and 5 of the source become elements 0, 1 and 2 of the result. It does in one instruction what is called left-packing or stream compaction: the vector form of a loop body such as if (a[i] > 0) b[j++] = a[i];, where a compare such as VPCMPD makes the mask and POPCNT of the mask, moved to a general-purpose register with KMOVW, says how far to advance j.

Register or memory#

• Register destination: the packed elements fill the low end; the rest keeps its old values, or becomes zero with {z}.
• Memory destination: only the packed elements are stored, one after another from the address, and the memory above them is not written. The store takes no {z}, as no EVEX store does.

Intel’s optimization guide compares four versions of such a loop (Section 17.5.1): with AVX2, a table of 256 index vectors for VPERMD and a masked store run 5.27 times as fast as scalar code; with AVX-512, VPCOMPRESSD into a register followed by an ordinary full-width store runs 11.9 times as fast. That version writes all 64 bytes and lets the next iteration overwrite what lies past the packed elements, so the output buffer needs room for a full vector at its end; the memory form avoids that and needs no extra space.

In compiled code#

GCC 14 and Clang 23 at -O2 emit it for the intrinsics, _mm512_maskz_compress_epi32 for the register form and _mm512_mask_compressstoreu_epi32 for the memory form, but did not vectorize such a loop for x86-64-v4: both kept it scalar.

VPEXPANDD does the reverse, spreading consecutive elements to the positions a mask selects. VCOMPRESSPS compresses singles, VPCOMPRESSQ quadwords, and AVX512_VBMI2’s VPCOMPRESSB bytes and words.

In the optimization guide

What the optimization guide says about VPCOMPRESSD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Vectors

• Shuffles and lane crossing: VPCOMPRESSD and VPEXPANDD replace shuffle tables, but compressing straight to memory is microcode on Zen 4 and Zen 5.

Golden Cove and Raptor Cove

• Vectors, AVX-512 and AMX: On Sapphire Rapids, VPCOMPRESSD to memory is four micro-ops in LLVM’s model, not a microcoded sequence as on Zen 4, so compressing straight into memory is fine here.

Zen 4

• Vectors and floating point: VPCOMPRESSD and the other compress instructions are microcoded when they write to memory: compressing into a register and then storing it is faster.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

j = 0
for i in range(VL // 32):
    if k1[i]:
        mem.d[j] = zmm2.d[i]
        j += 1
# the memory above element j is not written

j = 0
for i in range(VL // 32):
    if k1[i]:
        zmm1.d[j] = zmm2.d[i]
        j += 1
if zeroing:
    for i in range(j, VL // 32):
        zmm1.d[i] = 0
# else: the elements from j up keep their values
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPCOMPRESSD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPBROADCASTQ
• VPBROADCASTW
• VPCLMULQDQ
• VPCMPB
• VPCMPD
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW
• VPCMPGTB
• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPCMPQ
• VPCMPUB
• VPCMPUD
• VPCMPUQ
• VPCMPUW
• VPCMPW
• VPCOMPRESSB
• VPCOMPRESSQ
• VPCOMPRESSW
• VPCONFLICTD
• VPCONFLICTQ
• VPDPBUSD
• VPDPBUSDS
• VPDPWSSD
• VPDPWSSDS
• VPERMB
• VPERMD
• VPERMI2B
• VPERMI2D
• VPERMI2PD
• VPERMI2PS
• VPERMI2Q
• VPERMI2W
• VPERMILPD
• VPERMILPS
• VPERMPD
• VPERMPS

All 686 AVX10.1 instructions