VPCOMPRESSQ

VPCOMPRESSQ packs the quadwords that a mask selects at the low end of its destination, in their original order. VPCOMPRESSD describes the operation, its use for left-packing, and the register and memory destinations; VPCOMPRESSQ does the same for 2, 4 or 8 quadwords, int64_t, uint64_t or pointers, and VCOMPRESSPD for doubles. With eight elements to a ZMM register, the mask of a full vector fits in a byte.

What the cases show#

In the cases recorded on Zen 5:

• vpcompressq zmmword ptr [mem]{k3}, zmm24, with six of the eight mask bits set, stored the six selected elements in 48 bytes from the address and left the bytes after them untouched.
• vpcompressq zmm14{k6}, zmm8 packed elements 2, 5 and 7 into elements 0 to 2 and kept the old values of elements 3 to 7, as merge masking does; with {z}, vpcompressq ymm1{k5}{z}, ymm2 zeroed what lay above its single packed element.
• With no mask bit set within the vector length, the XMM memory form wrote nothing.

In compiled code#

GCC 14 and Clang 23 at -O2 emit it for _mm512_maskz_compress_epi64 and _mm512_mask_compressstoreu_epi64, moving the __mmask8 argument to K1 first, GCC with KMOVB and Clang with KMOVD. Neither vectorized a filtering loop such as if (a[i] > 0) d[j++] = a[i]; over int64_t for x86-64-v4. Both keep the memory form of the intrinsic with -march=znver5 as well, although AMD’s latency spreadsheet lists that form as microcoded on Zen 5, where the register form is two macro-ops with a latency of 2, 4 and 5 cycles for XMM, YMM and ZMM.

VPEXPANDQ spreads consecutive quadwords to the positions a mask selects, the reverse operation.

In the optimization guide

What the optimization guide says about VPCOMPRESSQ, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Zen 4

• Vectors and floating point: VPCOMPRESSD and the other compress instructions are microcoded when they write to memory: compressing into a register and then storing it is faster.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

j = 0
for i in range(VL // 64):
    if k1[i]:
        mem.q[j] = zmm2.q[i]
        j += 1
# the memory above element j is not written

j = 0
for i in range(VL // 64):
    if k1[i]:
        zmm1.q[j] = zmm2.q[i]
        j += 1
if zeroing:
    for i in range(j, VL // 64):
        zmm1.q[i] = 0
# else: the elements from j up keep their values
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPCOMPRESSQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPBROADCASTW
• VPCLMULQDQ
• VPCMPB
• VPCMPD
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW
• VPCMPGTB
• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPCMPQ
• VPCMPUB
• VPCMPUD
• VPCMPUQ
• VPCMPUW
• VPCMPW
• VPCOMPRESSB
• VPCOMPRESSD
• VPCOMPRESSW
• VPCONFLICTD
• VPCONFLICTQ
• VPDPBUSD
• VPDPBUSDS
• VPDPWSSD
• VPDPWSSDS
• VPERMB
• VPERMD
• VPERMI2B
• VPERMI2D
• VPERMI2PD
• VPERMI2PS
• VPERMI2Q
• VPERMI2W
• VPERMILPD
• VPERMILPS
• VPERMPD
• VPERMPS
• VPERMQ

All 686 AVX10.1 instructions