VPCOMPRESSW

VPCOMPRESSW packs the words that a mask selects into the low end of its destination, in their original order. It is the word sibling of VPCOMPRESSB, from the same extension, AVX512_VBMI2, and works as VPCOMPRESSD does, whose page explains left-packing and the two kinds of destination; VPEXPANDW is its reverse. A zmm register holds 32 words, so the mask is the low 32 bits of a mask register, moved with KMOVD and counted with POPCNT on 32 bits.

What the store writes#

To memory, VPCOMPRESSW writes two bytes per set mask bit and nothing else. In a case recorded on Zen 5, the xmm form under a mask whose low eight bits were E3h, five of them set, wrote 10 bytes and left the other six of the 16 as they were. So a stream of 16-bit values, such as audio samples or UTF-16 text, can be filtered in place without a spare vector at the end of the output. The 8-bit displacement of this form counts in words.

In compiled code#

GCC 14 and Clang 23 at -O2 emit it for the intrinsics, once VBMI2 is enabled (-mavx512vbmi2 or a -march that has it, not x86-64-v4). For a loop of 32 words per step that marks the nonzero ones with VPTESTMW, stores them with _mm512_mask_compressstoreu_epi16 and advances by the population count, both keep the memory form as written. Neither vectorized the scalar loop if (s[i] != 0) d[j++] = s[i];, even at -O3 for znver5.

AMD’s Zen 5 guide lists the register form as two macro-ops with a latency of 2, 4 and 5 cycles for xmm, ymm and zmm, and the memory form, like every compress to memory, as microcoded, without a latency. Where the output has room for a whole vector, the register form followed by an ordinary store avoids the microcode, as the VPCOMPRESSB page shows.

In the optimization guide

What the optimization guide says about VPCOMPRESSW, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Zen 4

• Vectors and floating point: VPCOMPRESSD and the other compress instructions are microcoded when they write to memory: compressing into a register and then storing it is faster.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

j = 0
for i in range(VL // 16):
    if k1[i]:
        mem.w[j] = zmm2.w[i]
        j += 1
# the memory above element j is not written

j = 0
for i in range(VL // 16):
    if k1[i]:
        zmm1.w[j] = zmm2.w[i]
        j += 1
if zeroing:
    for i in range(j, VL // 16):
        zmm1.w[i] = 0
# else: the elements from j up keep their values
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPCOMPRESSW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPCLMULQDQ
• VPCMPB
• VPCMPD
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW
• VPCMPGTB
• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPCMPQ
• VPCMPUB
• VPCMPUD
• VPCMPUQ
• VPCMPUW
• VPCMPW
• VPCOMPRESSB
• VPCOMPRESSD
• VPCOMPRESSQ
• VPCONFLICTD
• VPCONFLICTQ
• VPDPBUSD
• VPDPBUSDS
• VPDPWSSD
• VPDPWSSDS
• VPERMB
• VPERMD
• VPERMI2B
• VPERMI2D
• VPERMI2PD
• VPERMI2PS
• VPERMI2Q
• VPERMI2W
• VPERMILPD
• VPERMILPS
• VPERMPD
• VPERMPS
• VPERMQ
• VPERMT2B

All 686 AVX10.1 instructions