x86-64.net

Instruction

VPCOMPRESSW

Packs the words selected by a mask contiguously into the low end of a register or into memory.

Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VPCOMPRESSW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPCOMPRESSW m128 {k}, xmm VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512EVEX.128.66.0F38.W1 63 /rAVX10.1 or AVX512_VBMI2 + AVX512VL
VPCOMPRESSW xmm {k}{z}, xmm VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512EVEX.128.66.0F38.W1 63 /rAVX10.1 or AVX512_VBMI2 + AVX512VL
VPCOMPRESSW m256 {k}, ymm VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512EVEX.256.66.0F38.W1 63 /rAVX10.1 or AVX512_VBMI2 + AVX512VL
VPCOMPRESSW ymm {k}{z}, ymm VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512EVEX.256.66.0F38.W1 63 /rAVX10.1 or AVX512_VBMI2 + AVX512VL
VPCOMPRESSW m512 {k}, zmm VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512EVEX.512.66.0F38.W1 63 /rAVX10.1 or AVX512_VBMI2
VPCOMPRESSW zmm {k}{z}, zmm VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512EVEX.512.66.0F38.W1 63 /rAVX10.1 or AVX512_VBMI2

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPCOMPRESSW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_mask_compress_epi16 __m128i _mm_mask_compress_epi16(__m128i __S, __mmask8 __U, __m128i __D)

VPCOMPRESSW xmm {k}, xmm EVEX.128 -mavx512vl -mavx512vbmi2

_mm_mask_compressstoreu_epi16 void _mm_mask_compressstoreu_epi16(void *__P, __mmask8 __U, __m128i __D)

VPCOMPRESSW m128 {k}, xmm EVEX.128 -mavx512vl -mavx512vbmi2

_mm_maskz_compress_epi16 __m128i _mm_maskz_compress_epi16(__mmask8 __U, __m128i __D)

VPCOMPRESSW xmm {k}{z}, xmm EVEX.128 -mavx512vl -mavx512vbmi2

_mm256_mask_compress_epi16 __m256i _mm256_mask_compress_epi16(__m256i __S, __mmask16 __U, __m256i __D)

VPCOMPRESSW ymm {k}, ymm EVEX.256 -mavx512vl -mavx512vbmi2

_mm256_mask_compressstoreu_epi16 void _mm256_mask_compressstoreu_epi16(void *__P, __mmask16 __U, __m256i __D)

VPCOMPRESSW m256 {k}, ymm EVEX.256 -mavx512vl -mavx512vbmi2

_mm256_maskz_compress_epi16 __m256i _mm256_maskz_compress_epi16(__mmask16 __U, __m256i __D)

VPCOMPRESSW ymm {k}{z}, ymm EVEX.256 -mavx512vl -mavx512vbmi2

_mm512_mask_compress_epi16 __m512i _mm512_mask_compress_epi16(__m512i __S, __mmask32 __U, __m512i __D)

VPCOMPRESSW zmm {k}, zmm EVEX.512 -mavx512vbmi2

_mm512_mask_compressstoreu_epi16 void _mm512_mask_compressstoreu_epi16(void *__P, __mmask32 __U, __m512i __D)

VPCOMPRESSW m512 {k}, zmm EVEX.512 -mavx512vbmi2

_mm512_maskz_compress_epi16 __m512i _mm512_maskz_compress_epi16(__mmask32 __U, __m512i __D)

VPCOMPRESSW zmm {k}{z}, zmm EVEX.512 -mavx512vbmi2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512_VBMI2_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512_VBMI2 + AVX512VL
CPUID.(EAX=07H,ECX=0):ECX[6] AVX512_VBMI2
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512_VBMI2_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512_VBMI2 + AVX512VL
CPUID.(EAX=07H,ECX=0):ECX[6] AVX512_VBMI2
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512_VBMI2_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512_VBMI2
CPUID.(EAX=07H,ECX=0):ECX[6] AVX512_VBMI2

Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.