VPCONFLICTD

VPCONFLICTD compares each doubleword with every element below it in the same register: bit j of result element i is set when element j, for j less than i, equals element i. Element 0 is always 0, and an element whose value occurs only once below it gets one bit. For the indices 5, 3, 5, 5 the result is 0, 0, 1 and 101b. A write mask chooses which results are written, not which elements take part: an element left out by the mask still counts in the comparisons of those above it. It belongs to AVX512CD, with VPLZCNTD.

Why it exists#

A loop such as h[idx[i]] += v[i] cannot simply gather 16 values, add and scatter them back: when two of the indices are equal, the scatter keeps only one of the sums. VPCONFLICTD finds those repeats in one instruction. Intel’s optimization manual vectorizes a histogram this way (Section 17.16.1, Example 17-24):

1. VPCONFLICTD of the indices, then VPTESTMD of the result with itself and KORTESTW branch past the merging when no index repeats, the usual case for random input.
2. Otherwise VPLZCNTD and a subtraction from 31 turn each result into the position of the nearest equal element below, or -1, and a short loop of VPERMD and masked additions folds the repeated elements’ values together, a tree in a few steps.
3. Around these, VPGATHERDD loads the counts and VPSCATTERDD stores the sums.

The manual measures 1.11 times the speed of scalar code on random input and 1.34 times when all inputs are equal, modest gains for a loop that does little else. Its sparse dot product (Section 17.16.2, Example 17-25) puts eight indices of each of two vectors in one register, so that VPCONFLICTD finds the matching pairs, and reaches 4.4 times.

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 emit it for _mm512_conflict_epi32, but vectorize no histogram loop with it.

AMD’s Zen 5 guide lists the XMM form as one macro-op with a latency of 3 cycles, and the YMM and ZMM forms as two macro-ops with a latency of 7. VPCONFLICTQ compares quadwords.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    x = 0
    for j in range(i):
        if src2.d[j] == src2.d[i]:
            x |= 1 << j
    if k1[i]:
        zmm1.d[i] = x
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src2.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPCONFLICTD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPCMPB
• VPCMPD
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW
• VPCMPGTB
• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPCMPQ
• VPCMPUB
• VPCMPUD
• VPCMPUQ
• VPCMPUW
• VPCMPW
• VPCOMPRESSB
• VPCOMPRESSD
• VPCOMPRESSQ
• VPCOMPRESSW
• VPCONFLICTQ
• VPDPBUSD
• VPDPBUSDS
• VPDPWSSD
• VPDPWSSDS
• VPERMB
• VPERMD
• VPERMI2B
• VPERMI2D
• VPERMI2PD
• VPERMI2PS
• VPERMI2Q
• VPERMI2W
• VPERMILPD
• VPERMILPS
• VPERMPD
• VPERMPS
• VPERMQ
• VPERMT2B
• VPERMT2D

All 686 AVX10.1 instructions