VPCONFLICTQ

VPCONFLICTQ compares each quadword with every element below it in the same register: bit j of result element i is set when element j, for j less than i, equals element i, and the other bits are 0. With 8 elements in a ZMM register, the result uses at most bits 6:0. It is the quadword form of VPCONFLICTD, whose page explains the use: finding repeated indices before a gather and a scatter, as in a vectorized histogram. With 64-bit indices those are VPGATHERQQ and VPSCATTERQQ. The write mask chooses which results are written; every element still takes part in the comparisons. It belongs to AVX512CD, with VPLZCNTQ.

Recorded on Zen 5#

• Repeats. For the values A, B, A, C, C, B, B, A in ZMM30, vpconflictq zmm17{k6}, zmm30 wrote 1 for element 2, 10b for element 5 and 101b for element 7, the three K6 selects; the other five kept their old values.
• All equal. With one broadcast quadword, elements 0, 3, 6 and 7 became 0, 7, 3Fh and 7Fh: each has every element below it.
• The mask does not hide inputs. In vpconflictq ymm24{k2}{z}, ymm3, with the values D, E, D, F, element 2 repeats element 0 but K2 leaves it out, so the result was zero, as were elements 0 and 3, which have no equal below them.

In compiled code#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 compile _mm512_conflict_epi64 to one VPCONFLICTQ, but neither vectorizes h[ix[i] & 1023] += 1 over int64_t arrays: both keep the loop scalar.

AMD’s Zen 5 latency spreadsheet lists VPCONFLICTQ as VPCONFLICTD: one macro-op with 3 cycles for XMM registers, two macro-ops with 7 for YMM and ZMM ones, and four macro-ops for a YMM or ZMM source in memory.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    x = 0
    for j in range(i):
        if src2.q[j] == src2.q[i]:
            x |= 1 << j
    if k1[i]:
        zmm1.q[i] = x
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src2.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPCONFLICTQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPCMPD
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW
• VPCMPGTB
• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPCMPQ
• VPCMPUB
• VPCMPUD
• VPCMPUQ
• VPCMPUW
• VPCMPW
• VPCOMPRESSB
• VPCOMPRESSD
• VPCOMPRESSQ
• VPCOMPRESSW
• VPCONFLICTD
• VPDPBUSD
• VPDPBUSDS
• VPDPWSSD
• VPDPWSSDS
• VPERMB
• VPERMD
• VPERMI2B
• VPERMI2D
• VPERMI2PD
• VPERMI2PS
• VPERMI2Q
• VPERMI2W
• VPERMILPD
• VPERMILPS
• VPERMPD
• VPERMPS
• VPERMQ
• VPERMT2B
• VPERMT2D
• VPERMT2PD

All 686 AVX10.1 instructions