VPDPBSSD

VPDPBSSD is the dot-product step for bytes that are both signed. In each doubleword it multiplies the four signed bytes of the second operand by the four signed bytes of the third, adds the four products to the destination’s doubleword, and lets the sum wrap. VPDPBUSD, whose page explains the idea, takes one unsigned and one signed operand. AVX-VNNI-INT8 added the other combinations, each with a saturating twin:

VPDPBSUD is VPDPBUSD with its sources swapped. All of them share opcode 50h (51h for the saturating ones) and differ in the prefix: 66 for VPDPBUSD, F2 for VPDPBSSD, F3 for VPDPBSUD and none for VPDPBUUD.

A product of two signed bytes lies between -16256 (-128 times 127) and 16384 (-128 times -128), so a group of four sums to at most 65536 in magnitude: only the addition to the accumulator can overflow.

Two encodings#

• VEX (AVX-VNNI-INT8): xmm and ymm. Intel’s optimization manual lists it among the new instructions of the Crestmont E-core (Section 4.1.8.3).
• EVEX (AVX10.2): zmm as well, with masking and embedded broadcast.

Zen 5 has neither: its ten recorded cases, four VEX and six EVEX, all raised #UD.

In compiled code#

GCC 14 at -O2 with -march=arrowlake turns s += a[i] * b[i] over int8_t arrays into VPDPBSSD on ymm registers with a memory operand (and the same loop with uint8_t for a into VPDPBUSD), through pointer parameters as well when the count is a constant; a pointer loop of unknown length stays scalar at -O2 and becomes VPDPBSSD at -O3. Clang 23 does not use it even at -O3: it widens both arrays to words with VPMOVSXBW and multiplies pairs with VPMADDWD, the route it also takes for -march=znver5, which lacks VNNI-INT8. The intrinsic _mm256_dpbssd_epi32(acc, a, b) needs -mavxvnniint8; the 512-bit and masked ones need -mavx10.2.

In the optimization guide

What the optimization guide says about VPDPBSSD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Crestmont and Gracemont

• Vectors and AVX2: Crestmont runs the VNNI dot products at twice Gracemont’s rate.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not cpuid_leaf(7, 1)[3] >> 4 & 1:
    fault(UD)  # CPUID: no AVX-VNNI-INT8
for i in range(VL // 32):
    x = 0
    for j in range(4 * i, 4 * i + 4):
        x += ymm2.sb[j] * src3.sb[j]
    ymm1.d[i] = ymm1.d[i] + x
# ymm1 is zeroed from bit VL up

if not cpuid_leaf(7, 1)[3] >> 19 & 1:
    fault(UD)  # CPUID: no AVX10
ver = cpuid_leaf(0x24, 0)[1] & 0xFF
aux = cpuid_leaf(0x24, 1)[2] >> 2 & 1
if ver < 2 and not aux:
    fault(UD)  # neither AVX10.2 nor AVX10_V1_AUX
for i in range(VL // 32):
    x = 0
    for j in range(4 * i, 4 * i + 4):
        x += zmm2.sb[j] * src3.sb[j]
    if k1[i]:
        zmm1.d[i] = zmm1.d[i] + x
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPDPBSSD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX-VNNI-INT8 instructions

• VPDPBSSDS
• VPDPBSUD
• VPDPBSUDS
• VPDPBUUD
• VPDPBUUDS

More AVX10.2 instructions

• VFNMADD231BF16
• VFNMSUB132BF16
• VFNMSUB213BF16
• VFNMSUB231BF16
• VFPCLASSBF16
• VGETEXPBF16
• VGETMANTBF16
• VMAXBF16
• VMINBF16
• VMINMAXBF16
• VMINMAXPD
• VMINMAXPH
• VMINMAXPS
• VMINMAXSD
• VMINMAXSH
• VMINMAXSS
• VMOVD
• VMOVW
• VMPSADBW
• VMULBF16
• VPDPBSSDS
• VPDPBSUD
• VPDPBSUDS
• VPDPBUUD
• VPDPBUUDS
• VPDPWSUD
• VPDPWSUDS
• VPDPWUSD
• VPDPWUSDS
• VPDPWUUD
• VPDPWUUDS
• VRCPBF16
• VREDUCEBF16
• VRNDSCALEBF16
• VRSQRTBF16
• VSCALEFBF16
• VSQRTBF16
• VSUBBF16
• VUCOMXSD
• VUCOMXSH

All 96 AVX10.2 instructions