VPDPBSSDS

VPDPBSSDS computes what VPDPBSSD does, four products of the signed bytes of its second and third operands added to each doubleword of the destination, but clamps the final sum to the signed 32-bit range, 80000000h to 7FFFFFFFh, instead of letting it wrap. VPDPBSSD’s page has the table of the six instructions that AVX-VNNI-INT8 added and their prefixes; the saturating forms take opcode 51h where the wrapping ones take 50h, and VPDPBSSDS shares F2 with VPDPBSSD. Each product lies between -16,256 and 16,384, so the four of them sum to between -65,024 and 65,536 and only the addition to the accumulator can saturate. VPDPBUSDS, the AVX512_VNNI instruction, explains when saturation helps.

Two encodings#

• VEX (AVX-VNNI-INT8): XMM and YMM registers.
• EVEX (AVX10.2, or AVX10.1 with the AVX10_V1_AUX bit): ZMM as well, with masking and a broadcast doubleword.

Zen 5 has neither: its ten recorded cases, four VEX and six EVEX, all raised #UD.

In compiled code#

C has no saturating addition, so neither GCC 14 nor Clang 23 derives VPDPBSSDS from a loop: only the intrinsic gives it. _mm256_dpbssds_epi32(acc, a, b), with -mavxvnniint8, is one vpdpbssds ymm0, ymm1, ymm2 in both; the 512-bit intrinsics need -mavx10.2, which Clang 23 accepts and GCC 14 does not.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not cpuid_leaf(7, 1)[3] >> 4 & 1:
    fault(UD)  # CPUID: no AVX-VNNI-INT8
for i in range(VL // 32):
    x = 0
    for j in range(4 * i, 4 * i + 4):
        x += ymm2.sb[j] * src3.sb[j]
    ymm1.d[i] = ssat(ymm1.sd[i] + x, 32)
# ymm1 is zeroed from bit VL up

if not cpuid_leaf(7, 1)[3] >> 19 & 1:
    fault(UD)  # CPUID: no AVX10
ver = cpuid_leaf(0x24, 0)[1] & 0xFF
aux = cpuid_leaf(0x24, 1)[2] >> 2 & 1
if ver < 2 and not aux:
    fault(UD)  # neither AVX10.2 nor AVX10_V1_AUX
for i in range(VL // 32):
    x = 0
    for j in range(4 * i, 4 * i + 4):
        x += zmm2.sb[j] * src3.sb[j]
    if k1[i]:
        zmm1.d[i] = ssat(zmm1.sd[i] + x, 32)
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPDPBSSDS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX-VNNI-INT8 instructions

• VPDPBSSD
• VPDPBSUD
• VPDPBSUDS
• VPDPBUUD
• VPDPBUUDS

More AVX10.2 instructions

• VFNMSUB132BF16
• VFNMSUB213BF16
• VFNMSUB231BF16
• VFPCLASSBF16
• VGETEXPBF16
• VGETMANTBF16
• VMAXBF16
• VMINBF16
• VMINMAXBF16
• VMINMAXPD
• VMINMAXPH
• VMINMAXPS
• VMINMAXSD
• VMINMAXSH
• VMINMAXSS
• VMOVD
• VMOVW
• VMPSADBW
• VMULBF16
• VPDPBSSD
• VPDPBSUD
• VPDPBSUDS
• VPDPBUUD
• VPDPBUUDS
• VPDPWSUD
• VPDPWSUDS
• VPDPWUSD
• VPDPWUSDS
• VPDPWUUD
• VPDPWUUDS
• VRCPBF16
• VREDUCEBF16
• VRNDSCALEBF16
• VRSQRTBF16
• VSCALEFBF16
• VSQRTBF16
• VSUBBF16
• VUCOMXSD
• VUCOMXSH
• VUCOMXSS

All 96 AVX10.2 instructions