VPDPBSUD

VPDPBSUD multiplies, in each doubleword, the four signed bytes of its second operand by the four unsigned bytes of its third, adds the four products to the destination’s doubleword and lets the sum wrap. It is VPDPBUSD with the two byte operands swapped: that older instruction takes the unsigned bytes first. The opcode is the same 50h, told apart by an F3 prefix, and VPDPBSUDS clamps the sum to the signed 32-bit range instead. VPDPBSSD has the table of all four sign combinations of AVX-VNNI-INT8.

Each product lies between -32,640 (-128 times 255) and 32,385 (127 times 255), so their sum lies between -130,560 and 129,540, and only the addition to the accumulator can overflow.

Since only the order of the operands differs, a compiler that has VPDPBUSD can reach the same result by swapping them, and GCC 14 does: at -O2 with -march=arrowlake, s += a[i] * b[i] over an int8_t array a and a uint8_t array b becomes the VEX form of VPDPBUSD on ymm registers, with the signed array as the memory operand, written either way round in the source. Clang 23 widens the bytes to doublewords and accumulates with VPDPWSSD instead. Both compile _mm256_dpbsud_epi32(acc, a, b) to VPDPBSUD.

Two encodings#

• VEX (AVX-VNNI-INT8): xmm and ymm, whose intrinsics in Intel’s manual carry no _avx suffix, unlike those of AVX-VNNI’s VEX forms.
• EVEX (AVX10.2): zmm as well, with masking and a broadcast doubleword.

On Zen 5 all ten recorded cases, four VEX and six EVEX, raised #UD; the destination, the flags and MXCSR kept their values.

In the optimization guide

What the optimization guide says about VPDPBSUD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Crestmont and Gracemont

• Vectors and AVX2: Crestmont runs the VNNI dot products at twice Gracemont’s rate.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not cpuid_leaf(7, 1)[3] >> 4 & 1:
    fault(UD)  # CPUID: no AVX-VNNI-INT8
for i in range(VL // 32):
    x = 0
    for j in range(4 * i, 4 * i + 4):
        x += ymm2.sb[j] * src3.b[j]
    ymm1.d[i] = ymm1.d[i] + x
# ymm1 is zeroed from bit VL up

if not cpuid_leaf(7, 1)[3] >> 19 & 1:
    fault(UD)  # CPUID: no AVX10
ver = cpuid_leaf(0x24, 0)[1] & 0xFF
aux = cpuid_leaf(0x24, 1)[2] >> 2 & 1
if ver < 2 and not aux:
    fault(UD)  # neither AVX10.2 nor AVX10_V1_AUX
for i in range(VL // 32):
    x = 0
    for j in range(4 * i, 4 * i + 4):
        x += zmm2.sb[j] * src3.b[j]
    if k1[i]:
        zmm1.d[i] = zmm1.d[i] + x
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPDPBSUD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX-VNNI-INT8 instructions

• VPDPBSSD
• VPDPBSSDS
• VPDPBSUDS
• VPDPBUUD
• VPDPBUUDS

More AVX10.2 instructions

• VFNMSUB132BF16
• VFNMSUB213BF16
• VFNMSUB231BF16
• VFPCLASSBF16
• VGETEXPBF16
• VGETMANTBF16
• VMAXBF16
• VMINBF16
• VMINMAXBF16
• VMINMAXPD
• VMINMAXPH
• VMINMAXPS
• VMINMAXSD
• VMINMAXSH
• VMINMAXSS
• VMOVD
• VMOVW
• VMPSADBW
• VMULBF16
• VPDPBSSD
• VPDPBSSDS
• VPDPBSUDS
• VPDPBUUD
• VPDPBUUDS
• VPDPWSUD
• VPDPWSUDS
• VPDPWUSD
• VPDPWUSDS
• VPDPWUUD
• VPDPWUUDS
• VRCPBF16
• VREDUCEBF16
• VRNDSCALEBF16
• VRSQRTBF16
• VSCALEFBF16
• VSQRTBF16
• VSUBBF16
• VUCOMXSD
• VUCOMXSH
• VUCOMXSS

All 96 AVX10.2 instructions