VPDPBUSD

VPDPBUSD is the core of quantized neural-network inference on x86. In each 32-bit element it multiplies four unsigned bytes of the first source by the four signed bytes at the same positions of the second, and adds the four products to the element of the destination. Without it the same step takes three instructions (VPMADDUBSW, VPMADDWD with a vector of ones, and VPADDD), and the first of them saturates its 16-bit pair sums, which VPDPBUSD never does. The sum into the accumulator wraps on overflow; VPDPBUSDS saturates it instead.

The instruction exists in two encodings with the same opcode:

• EVEX (AVX512_VNNI, now part of AVX10.1): 128-, 256- and 512-bit vectors, masking, embedded broadcast and 32 registers.
• VEX (AVX-VNNI): 128- and 256-bit only, without masking, for processors without AVX-512 such as Alder Lake. Intel’s intrinsics name the VEX forms separately, for example _mm256_dpbusd_avx_epi32.

In the optimization guide

What the optimization guide says about VPDPBUSD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Crestmont and Gracemont

• Vectors and AVX2: Crestmont runs the VNNI dot products at twice Gracemont’s rate.

Ice Lake to Rocket Lake

• Vectors and AVX-512: VPDPBUSD, which replaces a three-instruction sequence of byte multiplications and additions, gains only two times on the client parts against three times on the servers, because on the clients the older sequence’s addition can also use port 5.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    x = 0
    for j in range(4 * i, 4 * i + 4):
        x += zmm2.b[j] * src3.sb[j]
    if k1[i]:  # 1 without a write mask
        zmm1.d[i] = zmm1.d[i] + x
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPDPBUSD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX-VNNI instructions

• VPDPBUSDS
• VPDPWSSD
• VPDPWSSDS

More AVX10.1 instructions

• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW
• VPCMPGTB
• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPCMPQ
• VPCMPUB
• VPCMPUD
• VPCMPUQ
• VPCMPUW
• VPCMPW
• VPCOMPRESSB
• VPCOMPRESSD
• VPCOMPRESSQ
• VPCOMPRESSW
• VPCONFLICTD
• VPCONFLICTQ
• VPDPBUSDS
• VPDPWSSD
• VPDPWSSDS
• VPERMB
• VPERMD
• VPERMI2B
• VPERMI2D
• VPERMI2PD
• VPERMI2PS
• VPERMI2Q
• VPERMI2W
• VPERMILPD
• VPERMILPS
• VPERMPD
• VPERMPS
• VPERMQ
• VPERMT2B
• VPERMT2D
• VPERMT2PD
• VPERMT2PS

All 686 AVX10.1 instructions