VPDPBUSDS

VPDPBUSDS computes what VPDPBUSD does, four products of an unsigned byte of the first source and a signed byte of the second added to each doubleword of the destination, but clamps the final sum to the signed 32-bit range instead of letting it wrap. The four products and their sum are always exact: each sum lies between -130,560 and 129,540. Only the addition into the accumulator can overflow, and only after more than 16,000 steps in the same direction.

When the accumulator fills#

With wrapping, a sum that passes 2^31 - 1 turns into a large negative number; with saturation it stops at the limit, still wrong but on the right side. In cases recorded on Zen 5 with the VEX form, an accumulator of 7FFFFFFFh plus 2 stayed 7FFFFFFFh, and 80000000h plus -508 stayed 80000000h, where the wrapping form gives 80000001h and 7FFFFE04h. Saturation also makes the order of the additions matter, as with any clamped sum: splitting a dot product over several accumulators and adding them at the end gives the same result only when no partial sum reached a limit. The instruction sets no flag that would say whether one did.

Encodings and compilers#

It has the encodings of the wrapping form: EVEX forms in AVX512_VNNI (now AVX10.1), with masking and a broadcast doubleword, and VEX forms for xmm and ymm in AVX-VNNI. Zen 5 has both. GCC 14 and Clang 23 at -O2 with -march=znver5 compile _mm256_dpbusds_epi32 as well as _mm256_dpbusds_avx_epi32 to the shorter VEX encoding, printed with a {vex} prefix, and _mm512_dpbusds_epi32 to EVEX. Neither compiler vectorizes a C loop that clamps its sum: the instruction comes only from the intrinsics. VPDPWSSDS is the saturating word form, and AVX-VNNI-INT8’s VPDPBUUDS and VPDPBSSDS read both sources as unsigned or as signed.

AMD’s Zen 5 guide gives both forms the same timing, one macro-op with a latency of 4 cycles.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    x = 0
    for j in range(4 * i, 4 * i + 4):
        x += zmm2.b[j] * src3.sb[j]
    if k1[i]:  # 1 without a write mask
        zmm1.d[i] = ssat(zmm1.sd[i] + x, 32)
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPDPBUSDS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX-VNNI instructions

• VPDPBUSD
• VPDPWSSD
• VPDPWSSDS

More AVX10.1 instructions

• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW
• VPCMPGTB
• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPCMPQ
• VPCMPUB
• VPCMPUD
• VPCMPUQ
• VPCMPUW
• VPCMPW
• VPCOMPRESSB
• VPCOMPRESSD
• VPCOMPRESSQ
• VPCOMPRESSW
• VPCONFLICTD
• VPCONFLICTQ
• VPDPBUSD
• VPDPWSSD
• VPDPWSSDS
• VPERMB
• VPERMD
• VPERMI2B
• VPERMI2D
• VPERMI2PD
• VPERMI2PS
• VPERMI2Q
• VPERMI2W
• VPERMILPD
• VPERMILPS
• VPERMPD
• VPERMPS
• VPERMQ
• VPERMT2B
• VPERMT2D
• VPERMT2PD
• VPERMT2PS
• VPERMT2Q

All 686 AVX10.1 instructions