x86-64.net

Instruction

VPDPBUSDS

Multiplies unsigned bytes of the first source by signed bytes of the second and adds each group of four products to a 32-bit accumulator, saturating.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VPDPBUSDS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPDPBUSDS xmm, xmm, xmm VPDPBUSDS_XMMi32_XMMu32_XMMu32VEX.128.66.0F38.W0 51 /rAVX_VNNI
VPDPBUSDS xmm, xmm, m128 VPDPBUSDS_XMMi32_XMMu32_MEMu32VEX.128.66.0F38.W0 51 /rAVX_VNNI
VPDPBUSDS ymm, ymm, ymm VPDPBUSDS_YMMi32_YMMu32_YMMu32VEX.256.66.0F38.W0 51 /rAVX_VNNI
VPDPBUSDS ymm, ymm, m256 VPDPBUSDS_YMMi32_YMMu32_MEMu32VEX.256.66.0F38.W0 51 /rAVX_VNNI
VPDPBUSDS xmm {k}{z}, xmm, xmm VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512EVEX.128.66.0F38.W0 51 /rAVX10.1 or AVX512_VNNI + AVX512VL
VPDPBUSDS xmm {k}{z}, xmm, m128/m32bcst VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512EVEX.128.66.0F38.W0 51 /rAVX10.1 or AVX512_VNNI + AVX512VL
VPDPBUSDS ymm {k}{z}, ymm, ymm VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512EVEX.256.66.0F38.W0 51 /rAVX10.1 or AVX512_VNNI + AVX512VL
VPDPBUSDS ymm {k}{z}, ymm, m256/m32bcst VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512EVEX.256.66.0F38.W0 51 /rAVX10.1 or AVX512_VNNI + AVX512VL
VPDPBUSDS zmm {k}{z}, zmm, zmm VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512EVEX.512.66.0F38.W0 51 /rAVX10.1 or AVX512_VNNI
VPDPBUSDS zmm {k}{z}, zmm, m512/m32bcst VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512EVEX.512.66.0F38.W0 51 /rAVX10.1 or AVX512_VNNI

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPDPBUSDS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_dpbusds_avx_epi32 __m128i _mm_dpbusds_avx_epi32(__m128i __S, __m128i __A, __m128i __B)

VPDPBUSDS xmm, xmm, xmm VEX.128 -mavxvnni

_mm_dpbusds_epi32 __m128i _mm_dpbusds_epi32(__m128i S, __m128i A, __m128i B)

VPDPBUSDS xmm, xmm, xmm EVEX.128 -mavx512vl -mavx512vnni

VPDPBUSDS xmm, xmm, xmm VEX.128 -mavxvnni

_mm_mask_dpbusds_epi32 __m128i _mm_mask_dpbusds_epi32(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B)

VPDPBUSDS xmm {k}, xmm, xmm EVEX.128 -mavx512vl -mavx512vnni

_mm_maskz_dpbusds_epi32 __m128i _mm_maskz_dpbusds_epi32(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B)

VPDPBUSDS xmm {k}{z}, xmm, xmm EVEX.128 -mavx512vl -mavx512vnni

_mm256_dpbusds_avx_epi32 __m256i _mm256_dpbusds_avx_epi32(__m256i __S, __m256i __A, __m256i __B)

VPDPBUSDS ymm, ymm, ymm VEX.256 -mavxvnni

_mm256_dpbusds_epi32 __m256i _mm256_dpbusds_epi32(__m256i S, __m256i A, __m256i B)

VPDPBUSDS ymm, ymm, ymm EVEX.256 -mavx512vl -mavx512vnni

VPDPBUSDS ymm, ymm, ymm VEX.256 -mavxvnni

_mm256_mask_dpbusds_epi32 __m256i _mm256_mask_dpbusds_epi32(__m256i __S, __mmask8 __U, __m256i __A, __m256i __B)

VPDPBUSDS ymm {k}, ymm, ymm EVEX.256 -mavx512vl -mavx512vnni

_mm256_maskz_dpbusds_epi32 __m256i _mm256_maskz_dpbusds_epi32(__mmask8 __U, __m256i __S, __m256i __A, __m256i __B)

VPDPBUSDS ymm {k}{z}, ymm, ymm EVEX.256 -mavx512vl -mavx512vnni

_mm512_dpbusds_epi32 __m512i _mm512_dpbusds_epi32(__m512i __S, __m512i __A, __m512i __B)

VPDPBUSDS zmm, zmm, zmm EVEX.512 -mavx512vnni

_mm512_mask_dpbusds_epi32 __m512i _mm512_mask_dpbusds_epi32(__m512i __S, __mmask16 __U, __m512i __A, __m512i __B)

VPDPBUSDS zmm {k}, zmm, zmm EVEX.512 -mavx512vnni

_mm512_maskz_dpbusds_epi32 __m512i _mm512_maskz_dpbusds_epi32(__mmask16 __U, __m512i __S, __m512i __A, __m512i __B)

VPDPBUSDS zmm {k}{z}, zmm, zmm EVEX.512 -mavx512vnni

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX_VNNI

AVX_VNNI
CPUID.(EAX=07H,ECX=1):EAX[4] AVX_VNNI

Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest
AVX512_VNNI_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512_VNNI + AVX512VL
CPUID.(EAX=07H,ECX=0):ECX[11] AVX512_VNNI
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Ice Lake (client), Tiger Lake, Nova Lake, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512_VNNI_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512_VNNI + AVX512VL
CPUID.(EAX=07H,ECX=0):ECX[11] AVX512_VNNI
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Ice Lake (client), Tiger Lake, Nova Lake, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512_VNNI_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512_VNNI
CPUID.(EAX=07H,ECX=0):ECX[11] AVX512_VNNI

Ice Lake (client), Tiger Lake, Nova Lake, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX-VNNI instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  4. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.