VPDPBUUD

VPDPBUUD is the dot-product step for two operands of unsigned bytes. In each doubleword it multiplies the four unsigned bytes of the second operand by the four unsigned bytes of the third, adds the four products to the destination’s doubleword, and lets the sum wrap modulo 2^32. VPDPBUSD explains the idea, and VPDPBSSD’s table shows the other sign combinations that AVX-VNNI-INT8 added; VPDPBUUD is the one with no prefix byte (opcode 50h), and VPDPBUUDS is its saturating twin, which clamps at FFFFFFFFh as an unsigned sum.

Before it, a dot product of two unsigned byte arrays could not use VPDPBUSD directly, since that instruction reads the bytes of its third operand as signed, and a value above 127 there would count as negative. A product of two unsigned bytes is at most 65,025 (255 times 255), and four of them at most 260,100, so again only the addition to the accumulator can overflow.

Two encodings#

• VEX (AVX-VNNI-INT8): xmm and ymm, which Intel’s optimization manual lists among the Crestmont E-core’s additions (Section 4.1.8.3).
• EVEX (AVX10.2): zmm as well, with masking and a broadcast doubleword.

Zen 5 has neither: its ten recorded cases, four VEX and six EVEX, all raised #UD and left the destination as it was.

In compiled code#

GCC 14 at -O2 with -march=arrowlake turns s += a[i] * b[i] over two uint8_t arrays of 1,024 elements into VPDPBUUD on ymm registers, one array read from memory. Clang 23 does not use it there: it widens both arrays to words with VPMOVZXBW and multiplies pairs with VPMADDWD. Both compile the intrinsic _mm256_dpbuud_epi32(acc, a, b), which needs -mavxvnniint8, to one VPDPBUUD.

In the optimization guide

What the optimization guide says about VPDPBUUD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Crestmont and Gracemont

• Vectors and AVX2: Crestmont runs the VNNI dot products at twice Gracemont’s rate.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not cpuid_leaf(7, 1)[3] >> 4 & 1:
    fault(UD)  # CPUID: no AVX-VNNI-INT8
for i in range(VL // 32):
    x = 0
    for j in range(4 * i, 4 * i + 4):
        x += ymm2.b[j] * src3.b[j]
    ymm1.d[i] = ymm1.d[i] + x
# ymm1 is zeroed from bit VL up

if not cpuid_leaf(7, 1)[3] >> 19 & 1:
    fault(UD)  # CPUID: no AVX10
ver = cpuid_leaf(0x24, 0)[1] & 0xFF
aux = cpuid_leaf(0x24, 1)[2] >> 2 & 1
if ver < 2 and not aux:
    fault(UD)  # neither AVX10.2 nor AVX10_V1_AUX
for i in range(VL // 32):
    x = 0
    for j in range(4 * i, 4 * i + 4):
        x += zmm2.b[j] * src3.b[j]
    if k1[i]:
        zmm1.d[i] = zmm1.d[i] + x
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPDPBUUD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX-VNNI-INT8 instructions

• VPDPBSSD
• VPDPBSSDS
• VPDPBSUD
• VPDPBSUDS
• VPDPBUUDS

More AVX10.2 instructions

• VFNMSUB132BF16
• VFNMSUB213BF16
• VFNMSUB231BF16
• VFPCLASSBF16
• VGETEXPBF16
• VGETMANTBF16
• VMAXBF16
• VMINBF16
• VMINMAXBF16
• VMINMAXPD
• VMINMAXPH
• VMINMAXPS
• VMINMAXSD
• VMINMAXSH
• VMINMAXSS
• VMOVD
• VMOVW
• VMPSADBW
• VMULBF16
• VPDPBSSD
• VPDPBSSDS
• VPDPBSUD
• VPDPBSUDS
• VPDPBUUDS
• VPDPWSUD
• VPDPWSUDS
• VPDPWUSD
• VPDPWUSDS
• VPDPWUUD
• VPDPWUUDS
• VRCPBF16
• VREDUCEBF16
• VRNDSCALEBF16
• VRSQRTBF16
• VSCALEFBF16
• VSQRTBF16
• VSUBBF16
• VUCOMXSD
• VUCOMXSH
• VUCOMXSS

All 96 AVX10.2 instructions