x86-64.net

Instruction

VPDPBUUD

Multiplies unsigned bytes by unsigned bytes, sums each group of four products and adds the sum to the matching 32-bit accumulator.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VPDPBUUD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPDPBUUD xmm, xmm, xmm VPDPBUUD_XMMu32_XMM4u8_XMM4u8VEX.128.NP.0F38.W0 50 /rAVX_VNNI_INT8
VPDPBUUD xmm, xmm, m128 VPDPBUUD_XMMu32_XMM4u8_MEM4u8VEX.128.NP.0F38.W0 50 /rAVX_VNNI_INT8
VPDPBUUD ymm, ymm, ymm VPDPBUUD_YMMu32_YMM4u8_YMM4u8VEX.256.NP.0F38.W0 50 /rAVX_VNNI_INT8
VPDPBUUD ymm, ymm, m256 VPDPBUUD_YMMu32_YMM4u8_MEM4u8VEX.256.NP.0F38.W0 50 /rAVX_VNNI_INT8
VPDPBUUD xmm {k}{z}, xmm, xmm VPDPBUUD_XMMu32_MASKmskw_XMM4u8_XMM4u8_AVX512EVEX.128.NP.0F38.W0 50 /rAVX10.2 or AVX10_V1_AUX
VPDPBUUD xmm {k}{z}, xmm, m128/m32bcst VPDPBUUD_XMMu32_MASKmskw_XMM4u8_MEM4u8_AVX512EVEX.128.NP.0F38.W0 50 /rAVX10.2 or AVX10_V1_AUX
VPDPBUUD ymm {k}{z}, ymm, ymm VPDPBUUD_YMMu32_MASKmskw_YMM4u8_YMM4u8_AVX512EVEX.256.NP.0F38.W0 50 /rAVX10.2 or AVX10_V1_AUX
VPDPBUUD ymm {k}{z}, ymm, m256/m32bcst VPDPBUUD_YMMu32_MASKmskw_YMM4u8_MEM4u8_AVX512EVEX.256.NP.0F38.W0 50 /rAVX10.2 or AVX10_V1_AUX
VPDPBUUD zmm {k}{z}, zmm, zmm VPDPBUUD_ZMMu32_MASKmskw_ZMM4u8_ZMM4u8_AVX512EVEX.512.NP.0F38.W0 50 /rAVX10.2 or AVX10_V1_AUX
VPDPBUUD zmm {k}{z}, zmm, m512/m32bcst VPDPBUUD_ZMMu32_MASKmskw_ZMM4u8_MEM4u8_AVX512EVEX.512.NP.0F38.W0 50 /rAVX10.2 or AVX10_V1_AUX

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPDPBUUD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_dpbuud_epi32 __m128i _mm_dpbuud_epi32(__m128i __W, __m128i __A, __m128i __B)

VPDPBUUD xmm, xmm, xmm VEX.128 -mavxvnniint8

VPDPBUUD xmm, xmm, xmm VEX.128 -mavx -mavxvnniint8with AVX enabled

_mm_mask_dpbuud_epi32 __m128i _mm_mask_dpbuud_epi32(__m128i __W, __mmask8 __U, __m128i __A, __m128i __B)

VPDPBUUD xmm {k}, xmm, xmm EVEX.128 -mavx10.2

_mm_maskz_dpbuud_epi32 __m128i _mm_maskz_dpbuud_epi32(__mmask8 __U, __m128i __W, __m128i __A, __m128i __B)

VPDPBUUD xmm {k}{z}, xmm, xmm EVEX.128 -mavx10.2

_mm256_dpbuud_epi32 __m256i _mm256_dpbuud_epi32(__m256i __W, __m256i __A, __m256i __B)

VPDPBUUD ymm, ymm, ymm VEX.256 -mavxvnniint8

VPDPBUUD ymm, ymm, ymm VEX.256 -mavx -mavxvnniint8with AVX enabled

_mm256_mask_dpbuud_epi32 __m256i _mm256_mask_dpbuud_epi32(__m256i __W, __mmask8 __U, __m256i __A, __m256i __B)

VPDPBUUD ymm {k}, ymm, ymm EVEX.256 -mavx10.2

_mm256_maskz_dpbuud_epi32 __m256i _mm256_maskz_dpbuud_epi32(__mmask8 __U, __m256i __W, __m256i __A, __m256i __B)

VPDPBUUD ymm {k}{z}, ymm, ymm EVEX.256 -mavx10.2

_mm512_dpbuud_epi32 __m512i _mm512_dpbuud_epi32(__m512i __W, __m512i __A, __m512i __B)

VPDPBUUD zmm, zmm, zmm EVEX.512 -mavx10.2

_mm512_mask_dpbuud_epi32 __m512i _mm512_mask_dpbuud_epi32(__m512i __W, __mmask16 __U, __m512i __A, __m512i __B)

VPDPBUUD zmm {k}, zmm, zmm EVEX.512 -mavx10.2

_mm512_maskz_dpbuud_epi32 __m512i _mm512_maskz_dpbuud_epi32(__mmask16 __U, __m512i __W, __m512i __A, __m512i __B)

VPDPBUUD zmm {k}{z}, zmm, zmm EVEX.512 -mavx10.2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX_VNNI_INT8

AVX_VNNI_INT8
CPUID.(EAX=07H,ECX=1):EDX[4] AVX_VNNI_INT8

Arrow Lake, Panther Lake, Nova Lake, Diamond Rapids, Sierra Forest, Clearwater Forest
AVX512_VNNI_INT8_128

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

or

AVX10_V1_AUX
CPUID.(EAX=24H,ECX=1):ECX[2] AVX10_V1_AUX

Nova Lake, Diamond Rapids
AVX512_VNNI_INT8_256

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

or

AVX10_V1_AUX
CPUID.(EAX=24H,ECX=1):ECX[2] AVX10_V1_AUX

Nova Lake, Diamond Rapids
AVX512_VNNI_INT8_512

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

or

AVX10_V1_AUX
CPUID.(EAX=24H,ECX=1):ECX[2] AVX10_V1_AUX

Nova Lake, Diamond Rapids

More AVX-VNNI-INT8 instructions

More AVX10.2 instructions

All 96 AVX10.2 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  4. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.