VPDPWSSD

VPDPWSSD is the word member of the VNNI dot products. In each 32-bit element it multiplies the two signed words of the first source by the two signed words at the same positions of the second, and adds both products to the doubleword already in the destination. That is VPMADDWD followed by VPADDD in one instruction, with the same result bit for bit: both wrap modulo 2^32, including PMADDWD’s single overflow when all four words are -32,768. Its byte sibling VPDPBUSD differs more from the sequence it replaces, which saturates at 16 bits.

Wrapping or saturating#

The addition into the accumulator wraps without a flag. In a case recorded on Zen 5 with the VEX form, an accumulator of 7FFFFFFFh plus the products 1 times 0 and 1 times 1 gave 80000000h. VPDPWSSDS clamps the sum to the signed 32-bit range instead. The other word variants of AVX-VNNI-INT16, VPDPWSUD, VPDPWUSD and their kin, read one or both sources as unsigned.

Two encodings#

The EVEX forms belong to AVX512_VNNI, now part of AVX10.1, with masking, broadcast of a doubleword and 512-bit vectors. AVX-VNNI has VEX forms for xmm and ymm only, whose intrinsics are named apart, for example _mm256_dpwssd_avx_epi32. Zen 5 has both: every VEX case recorded here ran. With both available, Clang 23 picks the shorter VEX encoding for ymm registers and prints it as {vex} vpdpwssd.

Where it appears#

Intel’s optimization manual suggests VPDPWSSD for inference where 8-bit data with VPDPBUSD costs too much accuracy, and expects no gain from it on client processors such as Ice Lake (Section 8.2.2).

Compilers use it for 16-bit dot products. For s += a[i] * b[i] over 1,024 int16_t pairs, GCC 14 at -O2 with -march=znver5 or -mavx512vnni emits VPDPWSSD on zmm registers, while Clang 23 keeps VPMADDWD and VPADDD. Clang uses it elsewhere: for a dot product of uint8_t and int8_t arrays it widens the bytes to words and accumulates with VPDPWSSD, where GCC emits VPDPBUSD, and for a rounded Q15 product it puts the rounding constant 4000h in the accumulator (see VPMULHRSW).

AMD’s Zen 5 guide lists VPDPWSSD as one macro-op with a latency of 4 cycles, as for VPDPBUSD.

In the optimization guide

What the optimization guide says about VPDPWSSD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Ice Lake to Rocket Lake

• Vectors and AVX-512: VPDPBUSD, which replaces a three-instruction sequence of byte multiplications and additions, gains only two times on the client parts against three times on the servers, because on the clients the older sequence’s addition can also use port 5.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    x = 0
    for j in range(2 * i, 2 * i + 2):
        x += zmm2.sw[j] * src3.sw[j]
    if k1[i]:  # 1 without a write mask
        zmm1.d[i] = zmm1.d[i] + x
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPDPWSSD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX-VNNI instructions

• VPDPBUSD
• VPDPBUSDS
• VPDPWSSDS

More AVX10.1 instructions

• VPCMPEQQ
• VPCMPEQW
• VPCMPGTB
• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPCMPQ
• VPCMPUB
• VPCMPUD
• VPCMPUQ
• VPCMPUW
• VPCMPW
• VPCOMPRESSB
• VPCOMPRESSD
• VPCOMPRESSQ
• VPCOMPRESSW
• VPCONFLICTD
• VPCONFLICTQ
• VPDPBUSD
• VPDPBUSDS
• VPDPWSSDS
• VPERMB
• VPERMD
• VPERMI2B
• VPERMI2D
• VPERMI2PD
• VPERMI2PS
• VPERMI2Q
• VPERMI2W
• VPERMILPD
• VPERMILPS
• VPERMPD
• VPERMPS
• VPERMQ
• VPERMT2B
• VPERMT2D
• VPERMT2PD
• VPERMT2PS
• VPERMT2Q
• VPERMT2W

All 686 AVX10.1 instructions