VPDPWSSDS

VPDPWSSDS computes what VPDPWSSD does, in each doubleword the two products of the signed words of the first source and the signed words at the same positions of the second, added to the doubleword already in the destination, but clamps that sum to the signed 32-bit range, 80000000h to 7FFFFFFFh, instead of letting it wrap. VPDPBUSDS, the byte form, shows when an accumulator fills and why a clamped sum, though wrong, keeps its sign. Like VPDPWSSD it has EVEX forms in AVX512_VNNI, with masking and a broadcast doubleword, and VEX forms for XMM and YMM registers in AVX-VNNI; Zen 5 runs both.

Recorded on Zen 5#

• Clamped above. With the VEX form, 7FFFFFFEh plus the products of two -1 by two -1, 2 in all, gave 7FFFFFFFh, and so did 7FFFFFFFh plus 7FFFh times 7FFFh.
• Clamped below. 80000001h plus 8 times 8 and -32768 times 32767 gave 80000000h, while 80000000h plus 7FFFh times 7FFFh rose to BFFF0001h without a clamp.
• A broadcast. In vpdpwssds zmm0{k7}, zmm31, dword bcst [mem], the words -1 and 0 of the broadcast took 7FFFFFFFh down to 7FFFFFF7h for a word of 8, and 0 to FFFF8001h for 7FFFh; the elements K7 leaves out kept their accumulators.

In compiled code#

Both compilers emit VPDPWSSDS for the intrinsics only: _mm512_dpwssds_epi32 gives the EVEX form on ZMM registers at -O2 with -march=znver5, and _mm256_dpwssds_avx_epi32 the VEX form, which GCC 14 and Clang 23 print as {vex} vpdpwssds. With both AVX-VNNI and AVX512VL, as on Zen 5, _mm256_dpwssds_epi32 also gives the shorter VEX encoding.

AMD’s Zen 5 latency spreadsheet gives one macro-op with a latency of 4 cycles, two per cycle on pipes FP0 and FP1, as for VPDPWSSD.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    x = 0
    for j in range(2 * i, 2 * i + 2):
        x += zmm2.sw[j] * src3.sw[j]
    if k1[i]:  # 1 without a write mask
        zmm1.d[i] = ssat(zmm1.sd[i] + x, 32)
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPDPWSSDS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX-VNNI instructions

• VPDPBUSD
• VPDPBUSDS
• VPDPWSSD

More AVX10.1 instructions

• VPCMPEQW
• VPCMPGTB
• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPCMPQ
• VPCMPUB
• VPCMPUD
• VPCMPUQ
• VPCMPUW
• VPCMPW
• VPCOMPRESSB
• VPCOMPRESSD
• VPCOMPRESSQ
• VPCOMPRESSW
• VPCONFLICTD
• VPCONFLICTQ
• VPDPBUSD
• VPDPBUSDS
• VPDPWSSD
• VPERMB
• VPERMD
• VPERMI2B
• VPERMI2D
• VPERMI2PD
• VPERMI2PS
• VPERMI2Q
• VPERMI2W
• VPERMILPD
• VPERMILPS
• VPERMPD
• VPERMPS
• VPERMQ
• VPERMT2B
• VPERMT2D
• VPERMT2PD
• VPERMT2PS
• VPERMT2Q
• VPERMT2W
• VPERMW

All 686 AVX10.1 instructions