x86-64.net

Instruction

VPDPWSUD

Multiplies signed words of the first source by unsigned words of the second and adds each pair of products to a 32-bit accumulator.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VPDPWSUD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPDPWSUD xmm, xmm, xmm VPDPWSUD_XMMi32_XMM2i16_XMM2u16VEX.128.F3.0F38.W0 D2 /rAVX_VNNI_INT16
VPDPWSUD xmm, xmm, m128 VPDPWSUD_XMMi32_XMM2i16_MEM2u16VEX.128.F3.0F38.W0 D2 /rAVX_VNNI_INT16
VPDPWSUD ymm, ymm, ymm VPDPWSUD_YMMi32_YMM2i16_YMM2u16VEX.256.F3.0F38.W0 D2 /rAVX_VNNI_INT16
VPDPWSUD ymm, ymm, m256 VPDPWSUD_YMMi32_YMM2i16_MEM2u16VEX.256.F3.0F38.W0 D2 /rAVX_VNNI_INT16
VPDPWSUD xmm {k}{z}, xmm, xmm VPDPWSUD_XMMi32_MASKmskw_XMM2i16_XMM2u16_AVX512EVEX.128.F3.0F38.W0 D2 /rAVX10.2 or AVX10_V1_AUX
VPDPWSUD xmm {k}{z}, xmm, m128/m32bcst VPDPWSUD_XMMi32_MASKmskw_XMM2i16_MEM2u16_AVX512EVEX.128.F3.0F38.W0 D2 /rAVX10.2 or AVX10_V1_AUX
VPDPWSUD ymm {k}{z}, ymm, ymm VPDPWSUD_YMMi32_MASKmskw_YMM2i16_YMM2u16_AVX512EVEX.256.F3.0F38.W0 D2 /rAVX10.2 or AVX10_V1_AUX
VPDPWSUD ymm {k}{z}, ymm, m256/m32bcst VPDPWSUD_YMMi32_MASKmskw_YMM2i16_MEM2u16_AVX512EVEX.256.F3.0F38.W0 D2 /rAVX10.2 or AVX10_V1_AUX
VPDPWSUD zmm {k}{z}, zmm, zmm VPDPWSUD_ZMMi32_MASKmskw_ZMM2i16_ZMM2u16_AVX512EVEX.512.F3.0F38.W0 D2 /rAVX10.2 or AVX10_V1_AUX
VPDPWSUD zmm {k}{z}, zmm, m512/m32bcst VPDPWSUD_ZMMi32_MASKmskw_ZMM2i16_MEM2u16_AVX512EVEX.512.F3.0F38.W0 D2 /rAVX10.2 or AVX10_V1_AUX

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPDPWSUD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_dpwsud_epi32 __m128i _mm_dpwsud_epi32(__m128i __W, __m128i __A, __m128i __B)

VPDPWSUD xmm, xmm, xmm VEX.128 -mavxvnniint16

VPDPWSUD xmm, xmm, xmm VEX.128 -mavx -mavxvnniint16with AVX enabled

_mm_mask_dpwsud_epi32 __m128i _mm_mask_dpwsud_epi32(__m128i __A, __mmask8 __U, __m128i __B, __m128i __C)

VPDPWSUD xmm {k}, xmm, xmm EVEX.128 -mavx10.2

_mm_maskz_dpwsud_epi32 __m128i _mm_maskz_dpwsud_epi32(__mmask8 __U, __m128i __A, __m128i __B, __m128i __C)

VPDPWSUD xmm {k}{z}, xmm, xmm EVEX.128 -mavx10.2

_mm256_dpwsud_epi32 __m256i _mm256_dpwsud_epi32(__m256i __W, __m256i __A, __m256i __B)

VPDPWSUD ymm, ymm, ymm VEX.256 -mavxvnniint16

VPDPWSUD ymm, ymm, ymm VEX.256 -mavx -mavxvnniint16with AVX enabled

_mm256_mask_dpwsud_epi32 __m256i _mm256_mask_dpwsud_epi32(__m256i __A, __mmask8 __U, __m256i __B, __m256i __C)

VPDPWSUD ymm {k}, ymm, ymm EVEX.256 -mavx10.2

_mm256_maskz_dpwsud_epi32 __m256i _mm256_maskz_dpwsud_epi32(__mmask8 __U, __m256i __A, __m256i __B, __m256i __C)

VPDPWSUD ymm {k}{z}, ymm, ymm EVEX.256 -mavx10.2

_mm512_dpwsud_epi32 __m512i _mm512_dpwsud_epi32(__m512i __A, __m512i __B, __m512i __C)

VPDPWSUD zmm, zmm, zmm EVEX.512 -mavx10.2

_mm512_mask_dpwsud_epi32 __m512i _mm512_mask_dpwsud_epi32(__m512i __A, __mmask16 __U, __m512i __B, __m512i __C)

VPDPWSUD zmm {k}, zmm, zmm EVEX.512 -mavx10.2

_mm512_maskz_dpwsud_epi32 __m512i _mm512_maskz_dpwsud_epi32(__mmask16 __U, __m512i __A, __m512i __B, __m512i __C)

VPDPWSUD zmm {k}{z}, zmm, zmm EVEX.512 -mavx10.2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX_VNNI_INT16

AVX_VNNI_INT16
CPUID.(EAX=07H,ECX=1):EDX[10] AVX_VNNI_INT16

Arrow Lake, Panther Lake, Nova Lake, Diamond Rapids, Clearwater Forest
AVX512_VNNI_INT16_128

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

or

AVX10_V1_AUX
CPUID.(EAX=24H,ECX=1):ECX[2] AVX10_V1_AUX

Nova Lake, Diamond Rapids
AVX512_VNNI_INT16_256

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

or

AVX10_V1_AUX
CPUID.(EAX=24H,ECX=1):ECX[2] AVX10_V1_AUX

Nova Lake, Diamond Rapids
AVX512_VNNI_INT16_512

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

or

AVX10_V1_AUX
CPUID.(EAX=24H,ECX=1):ECX[2] AVX10_V1_AUX

Nova Lake, Diamond Rapids

More AVX-VNNI-INT16 instructions

More AVX10.2 instructions

All 96 AVX10.2 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  4. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.