VPDPWSUD

VPDPWSUD multiplies, in each doubleword, the two signed words of its second operand by the two unsigned words of its third, adds both products to the destination’s doubleword and lets the sum wrap. It is the mixed-sign member of AVX-VNNI-INT16, which fills in the sign combinations that VPDPWSSD lacks:

The new six share opcode D2h (D3h when saturating) in map 0F38 and differ in the prefix: F3 for VPDPWSUD, 66 for VPDPWUSD, none for VPDPWUUD.

Two products can overflow#

Unlike the byte forms such as VPDPBSUD, the products here are large: each lies between -2,147,450,880 (-32,768 times 65,535) and 2,147,385,345 (32,767 times 65,535), so it fits a signed doubleword, but two of them need 33 bits. With an accumulator of 0, two products of -32,768 by 65,535 give 00010000h, a positive 65,536. VPDPWSUDS clamps the full sum instead.

Two encodings#

• VEX (AVX-VNNI-INT16): xmm and ymm.
• EVEX (AVX10.2, or AVX10.1 with the AVX10_V1_AUX bit): zmm as well, with masking and a broadcast doubleword.

Zen 5 has neither: its ten recorded cases, four VEX and six EVEX, all raised #UD.

In compiled code#

GCC 14 names the intrinsic _mm256_dpwsud_avx_epi32, Clang 23 and Intel’s manual _mm256_dpwsud_epi32, and each rejects the other’s name; both give one vpdpwsud ymm0, ymm1, ymm2. GCC 14 enables the extension for -march=arrowlake-s, lunarlake, pantherlake and clearwaterforest, not for arrowlake. For a loop of s += a[i] * b[i] over an int16_t array a and a uint16_t array b, it emits VPDPWUSD instead, the unsigned array in the register and the signed one in memory. Clang 23 widens both arrays to doublewords and multiplies with VPMULLD. With -mavx10.2, Clang 23 compiles _mm512_dpwsud_epi32 to the EVEX form on zmm registers.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not cpuid_leaf(7, 1)[3] >> 10 & 1:
    fault(UD)  # CPUID: no AVX-VNNI-INT16
for i in range(VL // 32):
    x = 0
    for j in range(2 * i, 2 * i + 2):
        x += ymm2.sw[j] * src3.w[j]
    ymm1.d[i] = ymm1.d[i] + x
# ymm1 is zeroed from bit VL up

if not cpuid_leaf(7, 1)[3] >> 19 & 1:
    fault(UD)  # CPUID: no AVX10
ver = cpuid_leaf(0x24, 0)[1] & 0xFF
aux = cpuid_leaf(0x24, 1)[2] >> 2 & 1
if ver < 2 and not aux:
    fault(UD)  # neither AVX10.2 nor AVX10_V1_AUX
for i in range(VL // 32):
    x = 0
    for j in range(2 * i, 2 * i + 2):
        x += zmm2.sw[j] * src3.w[j]
    if k1[i]:
        zmm1.d[i] = zmm1.d[i] + x
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPDPWSUD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX-VNNI-INT16 instructions

• VPDPWSUDS
• VPDPWUSD
• VPDPWUSDS
• VPDPWUUD
• VPDPWUUDS

More AVX10.2 instructions

• VFNMSUB132BF16
• VFNMSUB213BF16
• VFNMSUB231BF16
• VFPCLASSBF16
• VGETEXPBF16
• VGETMANTBF16
• VMAXBF16
• VMINBF16
• VMINMAXBF16
• VMINMAXPD
• VMINMAXPH
• VMINMAXPS
• VMINMAXSD
• VMINMAXSH
• VMINMAXSS
• VMOVD
• VMOVW
• VMPSADBW
• VMULBF16
• VPDPBSSD
• VPDPBSSDS
• VPDPBSUD
• VPDPBSUDS
• VPDPBUUD
• VPDPBUUDS
• VPDPWSUDS
• VPDPWUSD
• VPDPWUSDS
• VPDPWUUD
• VPDPWUUDS
• VRCPBF16
• VREDUCEBF16
• VRNDSCALEBF16
• VRSQRTBF16
• VSCALEFBF16
• VSQRTBF16
• VSUBBF16
• VUCOMXSD
• VUCOMXSH
• VUCOMXSS

All 96 AVX10.2 instructions