VPDPWSUDS

VPDPWSUDS computes what VPDPWSUD does, in each doubleword the two products of the signed words of its second operand by the unsigned words of its third, added to the destination’s doubleword, but clamps the sum to the signed 32-bit range, 80000000h to 7FFFFFFFh, instead of letting it wrap. VPDPWSUD’s page has the table of the AVX-VNNI-INT16 instructions; this one is opcode D3h with the F3 prefix.

The clamp sees the whole sum#

The two products together span -4,294,901,760 to 4,294,770,690, wider than a doubleword, and the clamp applies to the exact sum of both products and the accumulator. So, by Intel’s definition, an accumulator of 0 plus two products of 32,767 by 65,535 gives 7FFFFFFFh, where VPDPWSUD wraps to FFFD0002h (-196,606), and two products of -32,768 by 65,535 give 80000000h, where VPDPWSUD gives 00010000h. In VPDPWSSDS two products pass the range only when all four words are -32,768.

Two encodings#

• VEX (AVX-VNNI-INT16): XMM and YMM registers.
• EVEX (AVX10.2, or AVX10.1 with the AVX10_V1_AUX bit): ZMM as well, with masking and a broadcast doubleword.

Zen 5 has neither: its ten recorded cases, four VEX and six EVEX, all raised #UD.

GCC 14 calls the intrinsic _mm256_dpwsuds_avx_epi32 and Clang 23 _mm256_dpwsuds_epi32, the name in Intel’s manual; both compile it to one VPDPWSUDS.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not cpuid_leaf(7, 1)[3] >> 10 & 1:
    fault(UD)  # CPUID: no AVX-VNNI-INT16
for i in range(VL // 32):
    x = 0
    for j in range(2 * i, 2 * i + 2):
        x += ymm2.sw[j] * src3.w[j]
    ymm1.d[i] = ssat(ymm1.sd[i] + x, 32)
# ymm1 is zeroed from bit VL up

if not cpuid_leaf(7, 1)[3] >> 19 & 1:
    fault(UD)  # CPUID: no AVX10
ver = cpuid_leaf(0x24, 0)[1] & 0xFF
aux = cpuid_leaf(0x24, 1)[2] >> 2 & 1
if ver < 2 and not aux:
    fault(UD)  # neither AVX10.2 nor AVX10_V1_AUX
for i in range(VL // 32):
    x = 0
    for j in range(2 * i, 2 * i + 2):
        x += zmm2.sw[j] * src3.w[j]
    if k1[i]:
        zmm1.d[i] = ssat(zmm1.sd[i] + x, 32)
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPDPWSUDS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX-VNNI-INT16 instructions

• VPDPWSUD
• VPDPWUSD
• VPDPWUSDS
• VPDPWUUD
• VPDPWUUDS

More AVX10.2 instructions

• VFNMSUB132BF16
• VFNMSUB213BF16
• VFNMSUB231BF16
• VFPCLASSBF16
• VGETEXPBF16
• VGETMANTBF16
• VMAXBF16
• VMINBF16
• VMINMAXBF16
• VMINMAXPD
• VMINMAXPH
• VMINMAXPS
• VMINMAXSD
• VMINMAXSH
• VMINMAXSS
• VMOVD
• VMOVW
• VMPSADBW
• VMULBF16
• VPDPBSSD
• VPDPBSSDS
• VPDPBSUD
• VPDPBSUDS
• VPDPBUUD
• VPDPBUUDS
• VPDPWSUD
• VPDPWUSD
• VPDPWUSDS
• VPDPWUUD
• VPDPWUUDS
• VRCPBF16
• VREDUCEBF16
• VRNDSCALEBF16
• VRSQRTBF16
• VSCALEFBF16
• VSQRTBF16
• VSUBBF16
• VUCOMXSD
• VUCOMXSH
• VUCOMXSS

All 96 AVX10.2 instructions