VPDPWUSD

VPDPWUSD multiplies, in each doubleword, the two unsigned words of its second operand by the two signed words of its third, adds both products to the destination’s doubleword and lets the sum wrap. It is VPDPWSUD with the sources swapped, and that page has the table of all the AVX-VNNI-INT16 instructions and why two products can already overflow a doubleword; VPDPWUSDS clamps the sum instead. The opcode is D2h in map 0F38 with the 66 prefix, the prefix that marks the unsigned-by-signed VPDPBUSD among the byte forms.

Two encodings#

• VEX (AVX-VNNI-INT16): xmm and ymm.
• EVEX (AVX10.2, or AVX10.1 with the AVX10_V1_AUX bit): zmm as well, with masking and a broadcast doubleword.

Zen 5 has neither: its ten recorded cases, four VEX and six EVEX, all raised #UD.

In compiled code#

This is the form GCC 14 picks for mixed signs. At -O2 with -march=arrowlake-s, s += a[i] * b[i] over 1,024 elements of an int16_t and a uint16_t array becomes vpdpwusd ymm0, ymm1, ymmword ptr [mem] with the unsigned array loaded into ymm1 and the signed one as the memory operand, whichever way round the source writes them, as it turns the byte forms into VPDPBUSD. Clang 23 does not use it there: it widens both arrays with VPMOVSXWD and VPMOVZXWD and multiplies with VPMULLD. For the intrinsic GCC 14 has _mm256_dpwusd_avx_epi32 and Clang 23 _mm256_dpwusd_epi32, as in Intel’s manual; Clang 23 also has the EVEX forms with -mavx10.2.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not cpuid_leaf(7, 1)[3] >> 10 & 1:
    fault(UD)  # CPUID: no AVX-VNNI-INT16
for i in range(VL // 32):
    x = 0
    for j in range(2 * i, 2 * i + 2):
        x += ymm2.w[j] * src3.sw[j]
    ymm1.d[i] = ymm1.d[i] + x
# ymm1 is zeroed from bit VL up

if not cpuid_leaf(7, 1)[3] >> 19 & 1:
    fault(UD)  # CPUID: no AVX10
ver = cpuid_leaf(0x24, 0)[1] & 0xFF
aux = cpuid_leaf(0x24, 1)[2] >> 2 & 1
if ver < 2 and not aux:
    fault(UD)  # neither AVX10.2 nor AVX10_V1_AUX
for i in range(VL // 32):
    x = 0
    for j in range(2 * i, 2 * i + 2):
        x += zmm2.w[j] * src3.sw[j]
    if k1[i]:
        zmm1.d[i] = zmm1.d[i] + x
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPDPWUSD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX-VNNI-INT16 instructions

• VPDPWSUD
• VPDPWSUDS
• VPDPWUSDS
• VPDPWUUD
• VPDPWUUDS

More AVX10.2 instructions

• VFNMSUB132BF16
• VFNMSUB213BF16
• VFNMSUB231BF16
• VFPCLASSBF16
• VGETEXPBF16
• VGETMANTBF16
• VMAXBF16
• VMINBF16
• VMINMAXBF16
• VMINMAXPD
• VMINMAXPH
• VMINMAXPS
• VMINMAXSD
• VMINMAXSH
• VMINMAXSS
• VMOVD
• VMOVW
• VMPSADBW
• VMULBF16
• VPDPBSSD
• VPDPBSSDS
• VPDPBSUD
• VPDPBSUDS
• VPDPBUUD
• VPDPBUUDS
• VPDPWSUD
• VPDPWSUDS
• VPDPWUSDS
• VPDPWUUD
• VPDPWUUDS
• VRCPBF16
• VREDUCEBF16
• VRNDSCALEBF16
• VRSQRTBF16
• VSCALEFBF16
• VSQRTBF16
• VSUBBF16
• VUCOMXSD
• VUCOMXSH
• VUCOMXSS

All 96 AVX10.2 instructions