VPDPWUUD

VPDPWUUD multiplies, in each doubleword, the two unsigned words of its second operand by the two unsigned words of its third, adds both products to the destination’s doubleword and lets the sum wrap modulo 2^32. VPDPWSUD’s page has the table of the AVX-VNNI-INT16 instructions; this one is opcode D2h in map 0F38 with no prefix, and VPDPWUUDS is its saturating twin. Before it, VPMADDWD and VPDPWSSD read every word as signed, so a word above 7FFFh counted as negative.

Products near 2^32#

A product of two unsigned words is at most FFFE0001h (65,535 squared), just under 2^32, so two products alone can pass it: two such products sum to 1FFFC0002h and leave FFFC0002h. A dot product that must not wrap needs either VPDPWUUDS or inputs that keep the sum in range.

Two encodings#

• VEX (AVX-VNNI-INT16): xmm and ymm.
• EVEX (AVX10.2, or AVX10.1 with the AVX10_V1_AUX bit): zmm as well, with masking and a broadcast doubleword.

Zen 5 has neither: its ten recorded cases, four VEX and six EVEX, all raised #UD.

In compiled code#

At -O2 with -march=arrowlake-s, GCC 14 turns s += (unsigned)a[i] * b[i] over two uint16_t arrays of 1,024 elements, with an unsigned sum, into VPDPWUUD on ymm registers with one array as the memory operand; the cast matters, since two uint16_t promoted to int can overflow it. Clang 23 widens both arrays with VPMOVZXWD and multiplies with VPMULLD. The intrinsic is _mm256_dpwuud_avx_epi32 in GCC 14 and _mm256_dpwuud_epi32 in Clang 23 and Intel’s manual.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not cpuid_leaf(7, 1)[3] >> 10 & 1:
    fault(UD)  # CPUID: no AVX-VNNI-INT16
for i in range(VL // 32):
    x = 0
    for j in range(2 * i, 2 * i + 2):
        x += ymm2.w[j] * src3.w[j]
    ymm1.d[i] = ymm1.d[i] + x
# ymm1 is zeroed from bit VL up

if not cpuid_leaf(7, 1)[3] >> 19 & 1:
    fault(UD)  # CPUID: no AVX10
ver = cpuid_leaf(0x24, 0)[1] & 0xFF
aux = cpuid_leaf(0x24, 1)[2] >> 2 & 1
if ver < 2 and not aux:
    fault(UD)  # neither AVX10.2 nor AVX10_V1_AUX
for i in range(VL // 32):
    x = 0
    for j in range(2 * i, 2 * i + 2):
        x += zmm2.w[j] * src3.w[j]
    if k1[i]:
        zmm1.d[i] = zmm1.d[i] + x
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPDPWUUD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX-VNNI-INT16 instructions

• VPDPWSUD
• VPDPWSUDS
• VPDPWUSD
• VPDPWUSDS
• VPDPWUUDS

More AVX10.2 instructions

• VFNMSUB132BF16
• VFNMSUB213BF16
• VFNMSUB231BF16
• VFPCLASSBF16
• VGETEXPBF16
• VGETMANTBF16
• VMAXBF16
• VMINBF16
• VMINMAXBF16
• VMINMAXPD
• VMINMAXPH
• VMINMAXPS
• VMINMAXSD
• VMINMAXSH
• VMINMAXSS
• VMOVD
• VMOVW
• VMPSADBW
• VMULBF16
• VPDPBSSD
• VPDPBSSDS
• VPDPBSUD
• VPDPBSUDS
• VPDPBUUD
• VPDPBUUDS
• VPDPWSUD
• VPDPWSUDS
• VPDPWUSD
• VPDPWUSDS
• VPDPWUUDS
• VRCPBF16
• VREDUCEBF16
• VRNDSCALEBF16
• VRSQRTBF16
• VSCALEFBF16
• VSQRTBF16
• VSUBBF16
• VUCOMXSD
• VUCOMXSH
• VUCOMXSS

All 96 AVX10.2 instructions