VPDPWUUDS

VPDPWUUDS computes what VPDPWUUD does, two products of the unsigned words of its second and third operands added to each doubleword of the destination, but treats the doubleword as unsigned and stops at FFFFFFFFh instead of wrapping. It is the only member of AVX-VNNI-INT16 that saturates as unsigned, as VPDPBUUDS is among the byte forms; the others clamp at 7FFFFFFFh. The opcode is D3h in map 0F38 with no prefix, and VPDPWSUD’s page has the table of all six.

Only upward#

Both products are positive or zero, so the result never falls below the accumulator, and an accumulator of 80000000h counts as 2^31. Two products of 65,535 by 65,535 add 1FFFC0002h, more than a doubleword holds, so by Intel’s definition even an accumulator of 0 gives FFFFFFFFh, where VPDPWUUD keeps FFFC0002h. The clamp applies once, to the exact sum of the accumulator and both products.

Two encodings#

• VEX (AVX-VNNI-INT16): XMM and YMM registers.
• EVEX (AVX10.2, or AVX10.1 with the AVX10_V1_AUX bit): ZMM as well, with masking and a broadcast doubleword.

Zen 5 has neither: its ten recorded cases, four VEX and six EVEX, all raised #UD.

In compiled code#

GCC 14 compiles _mm_dpwuuds_avx_epi32(acc, a, b) to one vpdpwuuds xmm0, xmm1, xmm2, and Clang 23 does the same for _mm_dpwuuds_epi32, Intel’s name. With -mavx10.2, Clang 23 compiles the masked _mm512_mask_dpwuuds_epi32 to vpdpwuuds zmm0 {k1}, zmm1, zmm2.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not cpuid_leaf(7, 1)[3] >> 10 & 1:
    fault(UD)  # CPUID: no AVX-VNNI-INT16
for i in range(VL // 32):
    x = 0
    for j in range(2 * i, 2 * i + 2):
        x += ymm2.w[j] * src3.w[j]
    ymm1.d[i] = usat(ymm1.d[i] + x, 32)
# ymm1 is zeroed from bit VL up

if not cpuid_leaf(7, 1)[3] >> 19 & 1:
    fault(UD)  # CPUID: no AVX10
ver = cpuid_leaf(0x24, 0)[1] & 0xFF
aux = cpuid_leaf(0x24, 1)[2] >> 2 & 1
if ver < 2 and not aux:
    fault(UD)  # neither AVX10.2 nor AVX10_V1_AUX
for i in range(VL // 32):
    x = 0
    for j in range(2 * i, 2 * i + 2):
        x += zmm2.w[j] * src3.w[j]
    if k1[i]:
        zmm1.d[i] = usat(zmm1.d[i] + x, 32)
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPDPWUUDS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX-VNNI-INT16 instructions

• VPDPWSUD
• VPDPWSUDS
• VPDPWUSD
• VPDPWUSDS
• VPDPWUUD

More AVX10.2 instructions

• VFNMSUB132BF16
• VFNMSUB213BF16
• VFNMSUB231BF16
• VFPCLASSBF16
• VGETEXPBF16
• VGETMANTBF16
• VMAXBF16
• VMINBF16
• VMINMAXBF16
• VMINMAXPD
• VMINMAXPH
• VMINMAXPS
• VMINMAXSD
• VMINMAXSH
• VMINMAXSS
• VMOVD
• VMOVW
• VMPSADBW
• VMULBF16
• VPDPBSSD
• VPDPBSSDS
• VPDPBSUD
• VPDPBSUDS
• VPDPBUUD
• VPDPBUUDS
• VPDPWSUD
• VPDPWSUDS
• VPDPWUSD
• VPDPWUSDS
• VPDPWUUD
• VRCPBF16
• VREDUCEBF16
• VRNDSCALEBF16
• VRSQRTBF16
• VSCALEFBF16
• VSQRTBF16
• VSUBBF16
• VUCOMXSD
• VUCOMXSH
• VUCOMXSS

All 96 AVX10.2 instructions