VPERM2F128 instruction (AVX)

VPERM2F128 builds a ymm register from 128-bit halves: each half of the result is one of the four halves of its two sources, or zero. It is VPERM2I128 for AVX alone, and that page explains the immediate, a nibble per result half whose bits 1:0 choose a half, bit 3 writes zeros and bit 2 is not used, and how Clang replaces the instruction where something cheaper does the same.

What Zen 5 recorded

vperm2f128 ymm4, ymm4, ymmword ptr [mem], 0x9F set bit 3 in both nibbles and gave a zero register, whatever the sources held.
vperm2f128 ymm12, ymm6, ymm6, 0xA5 took ymm6’s high half for the low half of the result (5: bits 1:0 are 1, and bit 2 changed nothing) and zeroed the high half (0Ah has bit 3 set).

The lane crossing of AVX

Before AVX2 brought VPERMPD, VPERM2F128 was the only AVX instruction besides the inserts and extracts that moves doubles from one 128-bit lane to the other. GCC 14 and Clang 23 at -O2 show it:

Reversing four doubles is, with -mavx, VPERM2F128 to swap the halves and then VPERMILPD (GCC) or VSHUFPD (Clang) with 5 to swap within them. GCC writes the swap with the immediate 21h and Clang with 01h, the same result since both sources are one register. With -march=x86-64-v3 both use one VPERMPD with 1Bh, and VPERMPD with 4Eh for the swap alone.
Taking the high halves of two vectors, 31h, has no one-source replacement and stays VPERM2F128 for both targets.
For a[i] = b[i + 1] - b[i], Clang 23 with -march=x86-64-v3 loads each four doubles once and builds the vector shifted by one element from two neighbours, with VPERM2F128 21h and VSHUFPD; GCC 14 keeps that loop scalar.

AMD’s Zen 5 guide lists VPERM2F128 and VPERM2I128 alike, one macro-op on the pipes FP1 and FP2 with a latency of 3 cycles, against 1 for VINSERTF128.

In the optimization guide

What the optimization guide says about VPERM2F128, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Vectors

Shuffles and lane crossing: Most 256-bit AVX instructions stay within 128-bit lanes, and loading each lane with VINSERTF128 avoids shuffles across them.

Crestmont and Gracemont

Vectors and AVX2: Shuffles that move data across the 128-bit halves are slower: VPERM2I128, VPERM2F128, VPERMD, VPERMQ, VPERMPS and VPERMPD on 256 bits are two micro-ops with a latency of 7 cycles, the second holding a port for two cycles.

Zen and Zen+

Vectors and floating point: VPERM2F128 is microcoded, three cycles in AMD’s spreadsheet and eight macro-ops in LLVM’s model, while VINSERTF128 and VEXTRACTF128, which move one 128-bit half, take a cycle; moving halves with them beats a full permute. sources differ

Forms

Every encoding of VPERM2F128 that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VPERM2F128 ymm, ymm, m256, imm8` VPERM2F128_YMMqq_YMMqq_MEMqq_IMMb	`VEX.256.66.0F3A.W0 06 /r ib`	AVX
`VPERM2F128 ymm, ymm, ymm, imm8` VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb	`VEX.256.66.0F3A.W0 06 /r ib`	AVX

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

128-bit blocks by immediate: each half of the result is one of the four 128-bit halves of ymm2 and ymm3, or zero, as four bits of imm8 say.

Example: imm8 = 0x21 (0010 0001 in binary).

With imm8 = 0x21, result doubles 3 to 0: b1, b0, a3, a2.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for h in range(2):
    x = imm8 >> 4 * h & 15
    if x & 8:
        ymm1.dq[h] = 0
    elif x & 2:
        ymm1.dq[h] = src3.dq[x & 1]
    else:
        ymm1.dq[h] = ymm2.dq[x & 1]
# ymm1 is zeroed from bit 256 up

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VPERM2F128 ymm, ymm, ymm/m256, imm8`
`ymm`	explicit	write
`ymm`	explicit	read
`ymm/m256`	explicit	read
`imm8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: avx-type-6

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPERM2F128, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm256_permute2f128_pd` `__m256d _mm256_permute2f128_pd(__m256d V1, __m256d V2, const int M)`	`VPERM2F128 ymm, ymm, m256, imm8` VEX.256 -mavxwhen V2 comes from memory
`_mm256_permute2f128_ps` `__m256 _mm256_permute2f128_ps(__m256 V1, __m256 V2, const int M)`	`VPERM2F128 ymm, ymm, m256, imm8` VEX.256 -mavxwhen V2 comes from memory
`_mm256_permute2f128_si256` `__m256i _mm256_permute2f128_si256(__m256i V1, __m256i V2, const int M)`	`VPERM2F128 ymm, ymm, m256, imm8` VEX.256 -mavxwhen V2 comes from memory

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVX` AVX	AVX `CPUID.01H:ECX[28]` AVX	Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions

What Zen 5 recorded#

The lane crossing of AVX#