VPERM2I128 instruction (AVX2)

VPERM2I128 builds a YMM register from 128-bit halves: each half of the result is one of the four halves of its two sources, or zero. The immediate has a nibble per result half, low nibble for the low half: bits 1:0 choose the block (0 and 1 the low and high half of the first source, 2 and 3 those of the second), bit 3 writes zeros instead, and bit 2 is not used. So 0x20 joins the two low halves, 0x31 the two high ones, 0x21 takes the high half of the first source and the low half of the second, and 0x01 with the same register twice swaps its halves.

It is the tool for the steps that in-lane shuffles leave: most AVX2 instructions work on each 128-bit lane separately, so code that needs data to cross between the lanes, such as a transpose or a byte shift of the whole register built on VPALIGNR, combines halves with it. The intrinsic is _mm256_permute2x128_si256.

What compilers make of it

GCC 14 at -O2 emits VPERM2I128 for the intrinsic whatever the immediate. Clang 23 replaces it with something cheaper or shorter when it can:

0x20, two low halves, becomes VINSERTI128; when the second source is in memory, that reads 16 bytes instead of 32.
A swap of one register’s halves becomes VPERMQ (or VPERMPD) with 0x4E.
Without integer instructions around it, Clang uses the floating-point twin VPERM2F128, an AVX instruction that does the same.

Intel’s optimization guide shows an 8x8 transpose that loads 128-bit halves with VINSERTF128 instead of combining 256-bit loads with VPERM2F128, which in the Sandy Bridge microarchitecture runs only on port 5, the port of the other shuffles (Section 15.11.2); in Crestmont it takes two micro-ops and seven cycles (Section 4.1.9.1).

There is no EVEX form. With AVX-512, VSHUFI64X2 and VSHUFI32X4 pick 128-bit blocks for ZMM registers, each half of the result from one source, with masking; only a zeroing mask makes them write zeros.

In the optimization guide

What the optimization guide says about VPERM2I128, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Crestmont and Gracemont

Vectors and AVX2: Shuffles that move data across the 128-bit halves are slower: VPERM2I128, VPERM2F128, VPERMD, VPERMQ, VPERMPS and VPERMPD on 256 bits are two micro-ops with a latency of 7 cycles, the second holding a port for two cycles.

Zen and Zen+

Vectors and floating point: VPERM2F128 is microcoded, three cycles in AMD’s spreadsheet and eight macro-ops in LLVM’s model, while VINSERTF128 and VEXTRACTF128, which move one 128-bit half, take a cycle; moving halves with them beats a full permute. sources differ

Forms

Every encoding of VPERM2I128 that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VPERM2I128 ymm, ymm, m256, imm8` VPERM2I128_YMMqq_YMMqq_MEMqq_IMMb	`VEX.256.66.0F3A.W0 46 /r ib`	AVX2
`VPERM2I128 ymm, ymm, ymm, imm8` VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb	`VEX.256.66.0F3A.W0 46 /r ib`	AVX2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

128-bit blocks by immediate: each half of the result is one of the four 128-bit halves of ymm2 and ymm3, or zero, as four bits of imm8 say.

Example: imm8 = 0x21 (0010 0001 in binary).

With imm8 = 0x21, result quadwords 3 to 0: b1, b0, a3, a2.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for h in range(2):
    x = imm8 >> 4 * h & 15
    if x & 8:
        ymm1.dq[h] = 0
    elif x & 2:
        ymm1.dq[h] = src3.dq[x & 1]
    else:
        ymm1.dq[h] = ymm2.dq[x & 1]
# ymm1 is zeroed from bit 256 up

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VPERM2I128 ymm, ymm, ymm/m256, imm8`
`ymm`	explicit	write
`ymm`	explicit	read
`ymm/m256`	explicit	read
`imm8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: avx-type-6

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPERM2I128, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm256_alignr_epi64` `__m256i _mm256_alignr_epi64(__m256i A, __m256i B, const int imm)`	`VPERM2I128 ymm, ymm, ymm, imm8` VEX.256 -mavx512vl
`_mm256_permute2x128_si256` `__m256i _mm256_permute2x128_si256(__m256i V1, __m256i V2, const int M)`	`VPERM2I128 ymm, ymm, m256, imm8` VEX.256 -mavx2when V2 comes from memory

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVX2` AVX2	AVX2 `CPUID.(EAX=07H,ECX=0):EBX[5]` AVX2	Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

More AVX2 instructions

All 138 AVX2 instructions

What compilers make of it#