VPERMD

VPERMD takes doublewords from anywhere in a vector: element i of the result is the element of the table operand that element i of the index operand numbers. AVX2 added it, with VPERMPS for singles, as a way to move doublewords freely across the two 128-bit halves of a YMM register, which VPSHUFD and VPSHUFB cannot do. Only the low three bits of each index count (four in the 512-bit form), so an index wraps around; unlike PSHUFB’s selectors, none writes zero. There is no 128-bit form; within one XMM register, VPERMILPS with an index vector or VPSHUFB does the job.

The order of the operands is a trap. In Intel’s syntax VPERMD ymm1, ymm2, ymm3/m256 takes the indices from ymm2 and the table from ymm3 or memory. The AVX2 intrinsic _mm256_permutevar8x32_epi32(table, indices) names them the other way round, while the AVX-512 intrinsics such as _mm512_permutexvar_epi32(indices, table) follow the instruction.

Typical uses:

• Fixed lane-crossing rearrangements with a constant index vector: reversing eight elements, rotating them, or interleaving the halves of a register.
• Left-packing. To keep only the elements that passed a comparison, code turns the comparison into an 8-bit mask, loads an index vector for that mask from a table of 256, and lets VPERMD move the chosen elements to the front. AVX-512 does this in one step with VPCOMPRESSD.
• Two tables. VPERMI2D and VPERMT2D of AVX-512 choose from the doublewords of two registers; Intel’s optimization manual notes that the first overwrites the index register and the second the first table.

The EVEX forms add masking and registers 16 to 31. GCC 14 at -O2 emits VPERMD for both intrinsics, while Clang 23 chooses between VPERMD and VPERMPS by the instructions around it, so integer code compiled with Clang may show VPERMPS.

In the optimization guide

What the optimization guide says about VPERMD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Vectors

• Shuffles and lane crossing: Lane-crossing permutes such as VPERMD take longer than in-lane shuffles such as VPSHUFB, and LLVM treats them as slow on Zen. sources differ

Crestmont and Gracemont

• Vectors and AVX2: Shuffles that move data across the 128-bit halves are slower: VPERM2I128, VPERM2F128, VPERMD, VPERMQ, VPERMPS and VPERMPD on 256 bits are two micro-ops with a latency of 7 cycles, the second holding a port for two cycles.

Golden Cove and Raptor Cove

• Vectors, AVX-512 and AMX: VPERMD, VPERMQ, VPERMPS, VPERMPD, VPMULLQ, vrange, vgetmant and the half-precision complex multiplications wait for the old value of their destination, which they then overwrite.

Ice Lake to Rocket Lake

• Vectors and AVX-512: Ice Lake adds an in-lane shuffle unit on port 1, while lane-crossing shuffles such as VPERMD stay on port 5.

Skylake to Cooper Lake

• Vectors on all parts: Shuffles and permutes run on port 5 only, one a cycle; those that move data between 128-bit lanes, such as VPERMD, take three cycles.

Zen 2

• Vectors and floating point: AMD’s spreadsheet makes the AVX2 permutes that cross the 128-bit lanes, VPERMD, vpermps, vpermq and vpermpd, microcoded, while vperm2f128 is one macro-op of three cycles on pipe 2. sources differ

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

n = VL // 32   # 8 in ymm, 16 in zmm
for i in range(n):
    if k1[i]:  # 1 without a write mask
        zmm1.d[i] = src3.d[zmm2.d[i] % n]
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPERMD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX2 instructions

• VPAND
• VPANDN
• VPAVGB
• VPAVGW
• VPBLENDD
• VPBLENDVB
• VPBLENDW
• VPBROADCASTB
• VPBROADCASTD
• VPBROADCASTQ
• VPBROADCASTW
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW
• VPCMPGTB
• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPERM2I128
• VPERMPD
• VPERMPS
• VPERMQ
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPHADDD
• VPHADDSW
• VPHADDW
• VPHSUBD
• VPHSUBSW
• VPHSUBW
• VPMADDUBSW
• VPMADDWD
• VPMASKMOVD
• VPMASKMOVQ
• VPMAXSB
• VPMAXSD
• VPMAXSW

All 138 AVX2 instructions

More AVX10.1 instructions

• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPCMPQ
• VPCMPUB
• VPCMPUD
• VPCMPUQ
• VPCMPUW
• VPCMPW
• VPCOMPRESSB
• VPCOMPRESSD
• VPCOMPRESSQ
• VPCOMPRESSW
• VPCONFLICTD
• VPCONFLICTQ
• VPDPBUSD
• VPDPBUSDS
• VPDPWSSD
• VPDPWSSDS
• VPERMB
• VPERMI2B
• VPERMI2D
• VPERMI2PD
• VPERMI2PS
• VPERMI2Q
• VPERMI2W
• VPERMILPD
• VPERMILPS
• VPERMPD
• VPERMPS
• VPERMQ
• VPERMT2B
• VPERMT2D
• VPERMT2PD
• VPERMT2PS
• VPERMT2Q
• VPERMT2W
• VPERMW
• VPEXPANDB
• VPEXPANDD

All 686 AVX10.1 instructions