VPERMI2B

VPERMI2B looks up bytes in a table of two registers, its second and third operands, with the indices in its destination, which the bytes found then replace. It is the I form of the byte permutes of AVX512_VBMI: VPERMT2B, whose page covers the 128-entry table, the index bits and the compiler output, keeps the indices and overwrites the first table instead, and VPERMI2D explains the pair in general. Bit 6 of a zmm index picks the register, bits 5:0 the byte, and bit 7 is ignored; the ymm and xmm forms use 6 and 5 bits.

When the table stays#

The I form suits a table that is loaded once and used many times, because it destroys only the index, which is new on every pass anyway. Intel’s optimization manual looks up 64 input bytes per instruction this way, out[i] = table[in[i] & 127]: the 128-byte table sits in two registers for the whole loop, and each iteration loads 64 indices, runs VPERMI2B and stores the result (Section 17.17.2, Example 17-27). No AND with 127 is needed in the vector loop, since bit 7 is ignored. For the same loop written with _mm512_permutex2var_epi8(lo, idx, hi), GCC 14 and Clang 23 at -O2 with -march=znver5 pick VPERMI2B, as the table must survive; Clang also unrolls it eight times.

The manual’s two descriptions#

The manual’s figure for VPERMI2B (Figure 17-19) has an index of 65 fetch byte 1 of the second table, as Intel’s instruction reference defines it. The C-style operation printed beside it tests the index the other way round, taking indices above 63 from the first table. The figure is the right one: the page’s pseudocode follows the instruction reference, and Zen 5’s six recorded cases, one per form, agree with it.

Masks#

Under merge masking an unselected byte keeps its index, not a table byte; _mm512_mask2_permutex2var_epi8, with the mask after the index argument, is this form. With zero masking the I and T forms give the same result. AMD’s Zen 5 guide lists VPERMI2B as one macro-op with a latency of 3, 4 and 5 cycles for xmm, ymm and zmm, the same as VPERMT2B and VPERMB. VPERMI2W is the word version, for processors with AVX512BW but no VBMI.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

n = VL // 8            # 16 in xmm, 32 in ymm, 64 in zmm
for i in range(n):
    if k1[i]:
        x = zmm1.b[i]  # the index, in zmm1
        if x & n:
            zmm1.b[i] = src3.b[x % n]
        else:
            zmm1.b[i] = zmm2.b[x % n]
    elif zeroing:
        zmm1.b[i] = 0
    # else: zmm1.b[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPERMI2B, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPCMPGTQ
• VPCMPGTW
• VPCMPQ
• VPCMPUB
• VPCMPUD
• VPCMPUQ
• VPCMPUW
• VPCMPW
• VPCOMPRESSB
• VPCOMPRESSD
• VPCOMPRESSQ
• VPCOMPRESSW
• VPCONFLICTD
• VPCONFLICTQ
• VPDPBUSD
• VPDPBUSDS
• VPDPWSSD
• VPDPWSSDS
• VPERMB
• VPERMD
• VPERMI2D
• VPERMI2PD
• VPERMI2PS
• VPERMI2Q
• VPERMI2W
• VPERMILPD
• VPERMILPS
• VPERMPD
• VPERMPS
• VPERMQ
• VPERMT2B
• VPERMT2D
• VPERMT2PD
• VPERMT2PS
• VPERMT2Q
• VPERMT2W
• VPERMW
• VPEXPANDB
• VPEXPANDD
• VPEXPANDQ

All 686 AVX10.1 instructions