VPERMI2PD

VPERMI2PD picks doubles from a table of two registers, with the indices in the destination, which the results then overwrite. It is the I form of VPERMT2PD, which overwrites the first table instead, and VPERMI2D explains the pair. Per quadword index, bits 2:0 pick the element and bit 3 the table at 512 bits, one bit fewer for each halving of the width. The doubles move as bit patterns, so MXCSR plays no part.

Recorded on Zen 5#

• The index register is a table too. In vpermi2pd zmm7{k6}, zmm12, zmm7, ZMM7 held the indices and the second table: element 2’s index ended in 1011b and took ZMM7’s own old element 3, element 5’s ended in 0011b and took element 3 of ZMM12. The elements K6 left out kept their indices.
• Merging keeps the indices. In vpermi2pd zmm1{k7}, zmm2, qword bcst [mem], elements 2 to 4, left out by E3h, kept their index values, where a merging VPERMT2PD keeps the table; elements 1 and 5 to 7 had bit 3 set and took the broadcast double.
• Two bits at 128 bits. {evex} vpermi2pd xmm5, xmm5, xmm5 read indices ending in 1101b and 0101b; with bit 1 clear in both, both took element 1 of XMM5.

In compiled code#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 emit VPERMI2PD for _mm512_mask2_permutex2var_pd, whose unselected elements keep the index, and when the first table is still needed afterwards, as in _mm512_permutex2var_pd(a, idx, b) added to a. For a fixed shuffle of two vectors with __builtin_shufflevector, the odd elements or the interleave 0, 8, 1, 9 …, GCC loads the indices into the destination and uses VPERMI2PD, while Clang uses VPERMT2PD.

AMD’s Zen 5 latency spreadsheet gives VPERMI2PD 3, 4 and 5 cycles for XMM, YMM and ZMM registers, two per cycle on pipes FP1 and FP2.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

n = VL // 64           # 2 in xmm, 4 in ymm, 8 in zmm
for i in range(n):
    if k1[i]:
        x = zmm1.q[i]  # the index, in zmm1
        if x & n:
            zmm1.q[i] = src3.q[x % n]
        else:
            zmm1.q[i] = zmm2.q[x % n]
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src3.f64[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPERMI2PD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPCMPQ
• VPCMPUB
• VPCMPUD
• VPCMPUQ
• VPCMPUW
• VPCMPW
• VPCOMPRESSB
• VPCOMPRESSD
• VPCOMPRESSQ
• VPCOMPRESSW
• VPCONFLICTD
• VPCONFLICTQ
• VPDPBUSD
• VPDPBUSDS
• VPDPWSSD
• VPDPWSSDS
• VPERMB
• VPERMD
• VPERMI2B
• VPERMI2D
• VPERMI2PS
• VPERMI2Q
• VPERMI2W
• VPERMILPD
• VPERMILPS
• VPERMPD
• VPERMPS
• VPERMQ
• VPERMT2B
• VPERMT2D
• VPERMT2PD
• VPERMT2PS
• VPERMT2Q
• VPERMT2W
• VPERMW
• VPEXPANDB
• VPEXPANDD
• VPEXPANDQ
• VPEXPANDW
• VPEXTRB

All 686 AVX10.1 instructions