VPERMI2PS

VPERMI2PS picks singles from a table of two registers, with the indices in the destination, which the results then overwrite. It works as VPERMI2D does for doublewords, and that page explains the index bits, the I and T forms and how compilers choose between them; VPERMT2PS is the T form for singles. The elements are moved as 32-bit patterns: nothing is rounded or quieted, and the manual lists no floating-point exception for it, so MXCSR plays no part. Intel’s optimization manual introduces the two-source permutes with a drawing of this instruction (Section 17.8, Figure 17-10).

Indices in a float register#

The index vector is read as integers, even though the instruction otherwise works on singles, and only its low bits count: five for a ZMM table of 32 singles, four to pick the element and one the register, and one fewer per halving of the width. In the cases recorded on Zen 5, which used whatever bits the registers held:

• in vpermi2ps ymm9{k2}{z}, ymm9, ymm14, element 0 of YMM9 held C0B3A699h, about -5.614 as a single; its low four bits, 1001b, picked element 1 of YMM14, and other elements picked from YMM9 itself, the register serving as indices and first table at once;
• against a broadcast single, 8 of the 10 elements of ZMM24 that K4 selected had bit 4 set in their index and took the broadcast value, the other two came from ZMM3, and the 6 unselected elements kept their indices.

In compiled code#

For _mm512_permutex2var_ps(a, idx, b), GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 emit VPERMT2PS when a may be overwritten and VPERMI2PS when only the index register is free, and _mm512_mask2_permutex2var_ps, whose unselected elements keep the index, is always VPERMI2PS. For a fixed shuffle of two float vectors with __builtin_shufflevector, such as the interleave 0, 8, 1, 9 …, GCC loads the indices into the destination and uses VPERMI2PS, while Clang uses VPERMT2PS. Splitting complex floats into real and imaginary arrays depends on the count in GCC 14.2: with a constant count it is VPERMT2PS on zmm registers, and with a count known only at run time the loop stays scalar at -O2. Clang 23.1 uses VPERMT2PS on ymm registers in both cases.

AMD’s latency spreadsheet for Zen 5 lists it as one macro-op on pipes FP1 and FP2, with a latency of 3, 4 and 5 cycles for XMM, YMM and ZMM.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

n = VL // 32           # 4 in xmm, 8 in ymm, 16 in zmm
for i in range(n):
    if k1[i]:
        x = zmm1.d[i]  # the index, in zmm1
        if x & n:
            zmm1.d[i] = src3.d[x % n]
        else:
            zmm1.d[i] = zmm2.d[x % n]
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.f32[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPERMI2PS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPCMPUB
• VPCMPUD
• VPCMPUQ
• VPCMPUW
• VPCMPW
• VPCOMPRESSB
• VPCOMPRESSD
• VPCOMPRESSQ
• VPCOMPRESSW
• VPCONFLICTD
• VPCONFLICTQ
• VPDPBUSD
• VPDPBUSDS
• VPDPWSSD
• VPDPWSSDS
• VPERMB
• VPERMD
• VPERMI2B
• VPERMI2D
• VPERMI2PD
• VPERMI2Q
• VPERMI2W
• VPERMILPD
• VPERMILPS
• VPERMPD
• VPERMPS
• VPERMQ
• VPERMT2B
• VPERMT2D
• VPERMT2PD
• VPERMT2PS
• VPERMT2Q
• VPERMT2W
• VPERMW
• VPEXPANDB
• VPEXPANDD
• VPEXPANDQ
• VPEXPANDW
• VPEXTRB
• VPEXTRD

All 686 AVX10.1 instructions