VPERMI2Q

VPERMI2Q looks up quadwords in a table of two registers, the second and third operands, at the indices held in the destination, and overwrites the indices with the results. It is the quadword form of VPERMI2D, whose page explains the pair it forms with VPERMT2Q and the intrinsics that stand for both; the VPERMT2Q page gives the index bits for quadwords: bits 2:0 choose one of 8 elements of a ZMM register and bit 3 the register.

On Zen 5, vpermi2q zmm7{k3}, zmm12, qword bcst [mem] shows both halves of the table at work. The second table was one quadword repeated, so every index with bit 3 set returned that value, while the index 2 in element 3 fetched element 2 of ZMM12. K3 held EBh, and elements 2 and 4, left out by the mask, kept their indices: a merging VPERMI2Q falls back to the index, where VPERMT2Q keeps the table. vpermi2q xmm9, xmm9, xmm14 used XMM9 as indices and first table at once; the indices are read before they are overwritten.

In compiled code#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 compile _mm512_permutex2var_epi64(a, idx, b) to VPERMI2Q when idx is a register the function no longer needs, and to VPERMT2Q when a is; _mm512_mask2_permutex2var_epi64, whose mask falls back to idx, is always VPERMI2Q. A table of sixteen 64-bit entries in memory fits the form well: both load the first half and give the second as the memory operand, vpermi2q zmm0, zmm1, zmmword ptr [rdi+64]. Written as a loop, out[i] = tab[idx[i] & 15], the same lookup stays scalar in GCC and becomes VPGATHERDQ in Clang; neither finds the permute.

For a fixed shuffle of two vectors, interleaving them with __builtin_shufflevector(a, b, 0, 8, 1, 9, ...) or taking their odd elements, GCC loads the constant indices into the destination and uses VPERMI2Q, Clang loads them into another register and uses VPERMT2Q over a.

AMD’s Zen 5 latency spreadsheet gives VPERMI2Q 3, 4 and 5 cycles for XMM, YMM and ZMM registers, two per cycle on pipes FP1 and FP2, the same as VPERMT2Q. Zen 5’s 6 recorded cases cover the register and memory forms, broadcast included, at all three widths.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

n = VL // 64           # 2 in xmm, 4 in ymm, 8 in zmm
for i in range(n):
    if k1[i]:
        x = zmm1.q[i]  # the index, in zmm1
        if x & n:
            zmm1.q[i] = src3.q[x % n]
        else:
            zmm1.q[i] = zmm2.q[x % n]
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src3.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPERMI2Q, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPCMPUD
• VPCMPUQ
• VPCMPUW
• VPCMPW
• VPCOMPRESSB
• VPCOMPRESSD
• VPCOMPRESSQ
• VPCOMPRESSW
• VPCONFLICTD
• VPCONFLICTQ
• VPDPBUSD
• VPDPBUSDS
• VPDPWSSD
• VPDPWSSDS
• VPERMB
• VPERMD
• VPERMI2B
• VPERMI2D
• VPERMI2PD
• VPERMI2PS
• VPERMI2W
• VPERMILPD
• VPERMILPS
• VPERMPD
• VPERMPS
• VPERMQ
• VPERMT2B
• VPERMT2D
• VPERMT2PD
• VPERMT2PS
• VPERMT2Q
• VPERMT2W
• VPERMW
• VPEXPANDB
• VPEXPANDD
• VPEXPANDQ
• VPEXPANDW
• VPEXTRB
• VPEXTRD
• VPEXTRQ

All 686 AVX10.1 instructions