VPERMI2W

VPERMI2W looks up words in a table of two registers, with the indices in the destination, which the results then replace. It works as VPERMI2D does, whose page explains the I and T forms and how compilers choose between them; VPERMT2W is the T form for words. A zmm register holds 32 words, so the table has 64 entries: bits 4:0 of an index pick the word and bit 5 the register, and the 10 bits above are ignored. The ymm and xmm forms use 5 and 4 index bits for tables of 32 and 16 words. The word forms belong to AVX512BW, so every processor with that extension has them, while the byte forms, VPERMI2B and VPERMT2B, wait for AVX512_VBMI.

Uses#

• Rearranging 16-bit data. Intel’s optimization manual transposes 8 by 8 matrices of 2-byte elements, each held in two zmm registers, with two VPERMI2Ws and two constant index vectors, and reports it 37.3 times as fast as scalar code and 2.7 times as fast as its AVX2 version of unpacks and lane permutes (Section 17.8.1, Example 17-17).
• Splitting channels. For l[i] = s[2*i]; r[i] = s[2*i+1]; on int16_t samples, Clang 23 at -O2 with -march=x86-64-v4 loads two vectors and separates them with two VPERMT2Ws, indices 0, 2, 4 … and 1, 3, 5 …; GCC 14 does the same at -O3 with -march=znver5 and keeps the loop scalar at -O2.
• Byte tables without VBMI. A table of 64 bytes, widened to words, fits in two registers, so bytes widened with VPMOVZXBW can be looked up 32 at a time and narrowed again with VPMOVWB. The same manual shows that version beside the one VPERMB that VBMI allows, which ran 6.5 times as fast (Section 17.17.1, Example 17-26).

For _mm512_permutex2var_epi16, GCC 14 and Clang 23 at -O2 emit VPERMT2W when the first table may be overwritten, and VPERMI2W for _mm512_mask2_permutex2var_epi16, whose unselected elements keep the index.

AMD’s Zen 5 guide lists VPERMI2W as one macro-op with a latency of 3, 4 and 5 cycles for xmm, ymm and zmm, the same as the doubleword and byte forms.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

n = VL // 16           # 8 in xmm, 16 in ymm, 32 in zmm
for i in range(n):
    if k1[i]:
        x = zmm1.w[i]  # the index, in zmm1
        if x & n:
            zmm1.w[i] = src3.w[x % n]
        else:
            zmm1.w[i] = zmm2.w[x % n]
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPERMI2W, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPCMPUQ
• VPCMPUW
• VPCMPW
• VPCOMPRESSB
• VPCOMPRESSD
• VPCOMPRESSQ
• VPCOMPRESSW
• VPCONFLICTD
• VPCONFLICTQ
• VPDPBUSD
• VPDPBUSDS
• VPDPWSSD
• VPDPWSSDS
• VPERMB
• VPERMD
• VPERMI2B
• VPERMI2D
• VPERMI2PD
• VPERMI2PS
• VPERMI2Q
• VPERMILPD
• VPERMILPS
• VPERMPD
• VPERMPS
• VPERMQ
• VPERMT2B
• VPERMT2D
• VPERMT2PD
• VPERMT2PS
• VPERMT2Q
• VPERMT2W
• VPERMW
• VPEXPANDB
• VPEXPANDD
• VPEXPANDQ
• VPEXPANDW
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW

All 686 AVX10.1 instructions