VPERMIL2PS instruction (XOP)

Forms

Every encoding of VPERMIL2PS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VPERMIL2PS xmm, xmm, m128, xmm, imm8` VPERMIL2PS_XMMdq_XMMdq_MEMdq_XMMdq_IMMb	`VEX.128.66.0F3A.W0 48 /r /is4`	XOP
`VPERMIL2PS xmm, xmm, xmm, xmm, imm8` VPERMIL2PS_XMMdq_XMMdq_XMMdq_XMMdq_IMMb	`VEX.128.66.0F3A.W0 48 /r /is4` `VEX.128.66.0F3A.W1 48 /r /is4`	XOP
`VPERMIL2PS ymm, ymm, m256, ymm, imm8` VPERMIL2PS_YMMqq_YMMqq_MEMqq_YMMqq_IMMb	`VEX.256.66.0F3A.W0 48 /r /is4`	XOP
`VPERMIL2PS ymm, ymm, ymm, ymm, imm8` VPERMIL2PS_YMMqq_YMMqq_YMMqq_YMMqq_IMMb	`VEX.256.66.0F3A.W0 48 /r /is4` `VEX.256.66.0F3A.W1 48 /r /is4`	XOP
`VPERMIL2PS xmm, xmm, xmm, m128, imm8` VPERMIL2PS_XMMdq_XMMdq_XMMdq_MEMdq_IMMb	`VEX.128.66.0F3A.W1 48 /r /is4`	XOP
`VPERMIL2PS ymm, ymm, ymm, m256, imm8` VPERMIL2PS_YMMqq_YMMqq_YMMqq_MEMqq_IMMb	`VEX.256.66.0F3A.W1 48 /r /is4`	XOP

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Permute from two sources within lanes: each single of the result is the single of its lane of ymm2 or, with bit 2 of its selector in ymm4 set, of ymm3 that bits 1:0 of the selector number; with imm8[1] set, it is zeroed where bit 3 of the selector differs from imm8[0].

Example selectors in ymm4 (element 0 on the right, in hex); only bits 3:0 count. Example: imm8 = 0x02, M2Z = 10b: the elements whose selector has bit 3 set are zeroed. No processor here has XOP: the example was not run, but worked out by the pseudocode below. Shown for the ymm form; the xmm form works the same on 4 singles.

With the example selectors and imm8 = 0x02, result singles 7 to 0: a4, b6, a5, b7, b0, 0, a2, b1.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

features = cpuid_leaf(0x80000001, 0)[2]
if not features >> 11 & 1:
    fault(UD)                    # CPUID: no XOP
for i in range(VL // 32):
    s = src4.d[i]                # the selector of element i
    j = i - i % 4 + (s & 3)      # in the lane of element i
    a = ymm2.d[j]
    b = src3.d[j]
    x = b if s & 4 else a
    m = s >> 3 & 1               # M
    if imm8 & 2 and m != imm8 & 1:
        x = 0                    # M2Z
    ymm1.d[i] = x
# ymm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 6 cases. Its cases ran where CPUID reported no XOP, and every one raised an exception.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VPERMIL2PS xmm, xmm, xmm/m128, xmm, imm8` `VPERMIL2PS ymm, ymm, ymm/m256, ymm, imm8`
`xmm, ymm`	explicit	write
`xmm, ymm`	explicit	read
`xmm/m128, ymm/m256`	explicit	read
`xmm, ymm`	explicit	read
`imm8`	explicit	read
`VPERMIL2PS xmm, xmm, xmm, m128, imm8` `VPERMIL2PS ymm, ymm, ymm, m256, imm8`
`xmm, ymm`	explicit	write
`xmm, ymm`	explicit	read
`xmm, ymm`	explicit	read
`m128/256`	explicit	read
`imm8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPERMIL2PS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_permute2_ps` `__m128 _mm_permute2_ps(__m128 X, __m128 Y, __m128i C, const int I)`	`VPERMIL2PS xmm, xmm, xmm, xmm, imm8` VEX.128 -mxop
`_mm256_permute2_ps` `__m256 _mm256_permute2_ps(__m256 X, __m256 Y, __m256i C, const int I)`	`VPERMIL2PS ymm, ymm, ymm, ymm, imm8` VEX.256 -mxop

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`XOP` XOP	XOP `CPUID.80000001H:ECX[11]` XOP	Bulldozer, Piledriver

More XOP instructions

All 55 XOP instructions