VPERMILPD

VPERMILPD chooses, for each double of the result, one of the two doubles of the same 128-bit lane of its source. It is the double-precision side of VPERMILPS, whose page covers the two kinds of control and the rule that no element leaves its lane; VPERMPD crosses lanes. With only two candidates per lane, each element needs one selector bit, and the two controls place it differently from the single-precision form.

Bit 1 of each quadword#

In the vector form, the bit that chooses is bit 1 of the matching quadword of the control; bit 0 and the other 62 bits are ignored. Zen 5’s recorded case vpermilpd ymm7, ymm11, ymm7 shows it with control quadwords ending in 2Ch, 36h, F2h and 99h: the first and the last, with bit 1 clear, took the low double of their lane, although 99h has bit 0 set; the other two took the high one. A control vector of indices 0 and 1, as VPERMILPS would read them, therefore selects the low double everywhere; indices must be doubled, 0 and 2.

One immediate bit per element#

The immediate form gives each element its own bit, not one pattern repeated per lane: bits 1:0 for an xmm register, 3:0 for ymm and all eight for zmm. vpermilpd ymm4, ymm4, 0x57 (bits 3:0 are 0111b) took element 1 into elements 0 and 1, element 3 into element 2 and element 2 into element 3, on Zen 5 as in the manuals. Swapping the two doubles of every lane is 1 for xmm and 5 for ymm.

In compiled code#

GCC 14 at -O2 with -mavx emits the immediate form for one-register shuffles of doubles within lanes: vpermilpd xmm0, xmm0, 1 for a swap, 5 for the swap in both lanes of a ymm register and 0 to repeat the low double of each lane. Clang 23 writes the swaps as VSHUFPD of a register with itself and the repeat as VMOVDDUP, and uses VPERMILPD when the source comes from memory, as with VPERMILPS. Both emit the vector form for _mm256_permutevar_pd. AMD’s Zen 5 guide gives the immediate form a latency of 1 cycle on all four vector pipes and the vector form 2 cycles on two.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:  # 1 without a write mask
        x = src3.q[i]
        j = i - i % 2 + (x >> 1 & 1)
        zmm1.q[i] = zmm2.q[j]
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src3.f64[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

for i in range(VL // 64):
    j = i - i % 2 + (imm8 >> i & 1)
    if k1[i]:  # 1 without a write mask
        zmm1.q[i] = src2.q[j]
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src2.f64[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-6

EVEX forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPERMILPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPAND
• VPANDN
• VPAVGB
• VPAVGW
• VPBLENDVB
• VPBLENDW
• VPCLMULQDQ
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW
• VPCMPESTRI
• VPCMPESTRM
• VPCMPGTB
• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPCMPISTRI
• VPCMPISTRM
• VPERM2F128
• VPERMILPS
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPHADDD
• VPHADDSW
• VPHADDW
• VPHMINPOSUW
• VPHSUBD
• VPHSUBSW
• VPHSUBW
• VPINSRB
• VPINSRD
• VPINSRQ
• VPINSRW
• VPMADDUBSW
• VPMADDWD
• VPMAXSB
• VPMAXSD

All 253 AVX instructions

More AVX10.1 instructions

• VPCMPUW
• VPCMPW
• VPCOMPRESSB
• VPCOMPRESSD
• VPCOMPRESSQ
• VPCOMPRESSW
• VPCONFLICTD
• VPCONFLICTQ
• VPDPBUSD
• VPDPBUSDS
• VPDPWSSD
• VPDPWSSDS
• VPERMB
• VPERMD
• VPERMI2B
• VPERMI2D
• VPERMI2PD
• VPERMI2PS
• VPERMI2Q
• VPERMI2W
• VPERMILPS
• VPERMPD
• VPERMPS
• VPERMQ
• VPERMT2B
• VPERMT2D
• VPERMT2PD
• VPERMT2PS
• VPERMT2Q
• VPERMT2W
• VPERMW
• VPEXPANDB
• VPEXPANDD
• VPEXPANDQ
• VPEXPANDW
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPGATHERDD

All 686 AVX10.1 instructions