VPERMILPS

VPERMILPS rearranges the singles of one source within each 128-bit lane, as PSHUFD does for doublewords. It has two kinds of control:

• An immediate, with two bits per element as in PSHUFD; in a YMM or ZMM register every lane uses the same four selectors.
• A vector, where the low two bits of each doubleword choose the single for that position from within its own lane, and the other 30 bits are ignored. Each element can have its own choice, chosen at run time.

No element ever leaves its lane: element 5 of a YMM result comes from elements 4 to 7 of the source. To move singles across lanes, AVX2 has VPERMPS, whose indices span the whole register.

Immediate or SHUFPS#

The immediate form computes what VSHUFPS does with the same register as both sources, but it can take that one source from memory, so a load and a shuffle become one instruction. Compilers use it that way: for _mm_shuffle_ps(a, a, imm) with -mavx, GCC 14 at -O2 emits VPERMILPS, while Clang 23 emits VSHUFPS for a register and VPERMILPS for a value loaded from memory. Intel’s optimization manual ends a horizontal sum of a YMM register with VEXTRACTF128 and two VPERMILPS, with immediates 0Eh and 01h, each followed by an addition (Section 15.15.1, Example 15-36).

The double version differs#

VPERMILPD, its counterpart for doubles, also takes one selector bit per element from a control vector, but bit 1 of each quadword rather than bit 0. Code that builds control vectors for both from the same index arithmetic gets the doubles wrong.

The EVEX form adds masking and a broadcast element from memory (the control vector in the vector form, the source in the immediate form). AMD’s XOP extension had VPERMIL2PS, which chooses from two sources and can zero elements; Zen 5 does not have XOP.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        x = src3.d[i]
        j = i - i % 4 + (x & 3)
        zmm1.d[i] = zmm2.d[j]
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.f32[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

for i in range(VL // 32):
    k = imm8 >> 2 * (i % 4) & 3
    j = i - i % 4 + k
    if k1[i]:  # 1 without a write mask
        zmm1.d[i] = src2.d[j]
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src2.f32[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-6

EVEX forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPERMILPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPANDN
• VPAVGB
• VPAVGW
• VPBLENDVB
• VPBLENDW
• VPCLMULQDQ
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW
• VPCMPESTRI
• VPCMPESTRM
• VPCMPGTB
• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPCMPISTRI
• VPCMPISTRM
• VPERM2F128
• VPERMILPD
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPHADDD
• VPHADDSW
• VPHADDW
• VPHMINPOSUW
• VPHSUBD
• VPHSUBSW
• VPHSUBW
• VPINSRB
• VPINSRD
• VPINSRQ
• VPINSRW
• VPMADDUBSW
• VPMADDWD
• VPMAXSB
• VPMAXSD
• VPMAXSW

All 253 AVX instructions

More AVX10.1 instructions

• VPCMPW
• VPCOMPRESSB
• VPCOMPRESSD
• VPCOMPRESSQ
• VPCOMPRESSW
• VPCONFLICTD
• VPCONFLICTQ
• VPDPBUSD
• VPDPBUSDS
• VPDPWSSD
• VPDPWSSDS
• VPERMB
• VPERMD
• VPERMI2B
• VPERMI2D
• VPERMI2PD
• VPERMI2PS
• VPERMI2Q
• VPERMI2W
• VPERMILPD
• VPERMPD
• VPERMPS
• VPERMQ
• VPERMT2B
• VPERMT2D
• VPERMT2PD
• VPERMT2PS
• VPERMT2Q
• VPERMT2W
• VPERMW
• VPEXPANDB
• VPEXPANDD
• VPEXPANDQ
• VPEXPANDW
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPGATHERDD
• VPGATHERDQ

All 686 AVX10.1 instructions