VPERMPD

VPERMPD rearranges the doubles of a vector across its 128-bit lanes. It is the double-precision twin of VPERMQ, whose page covers the two forms, the common immediates and how Clang picks between the two; the data are only moved, so no floating-point exception or MXCSR flag is possible. There is no 128-bit form: within one xmm register, VPERMILPD does the job.

In code on doubles#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v3 use the immediate form whenever four doubles of a ymm register are rearranged:

• copying an array of doubles backwards is VPERMPD with 0x1B (27), reading straight from memory;
• repeating element 2 of a vector everywhere is 0xAA (170), and rotating the four elements by one is 0x39 (57).

Eight doubles in a zmm register are another matter, because the immediate form of 512 bits rearranges each 256-bit half on its own. For reversing a zmm vector, both compilers with -march=x86-64-v4 load an index vector and use the form that takes it from a register; for the reversed copy, GCC does the same on zmm registers and Clang keeps four immediate VPERMPD on ymm ones.

On Zen 5#

The cases recorded on Zen 5 show both points:

• vpermpd zmm24{k7}, zmm3, 0xA6 took elements 2, 1, 2 and 2 of each half of zmm3 for that half, in the elements that k7 selected.
• vpermpd zmm24{k7}, zmm3, zmm3, with the same register as indices and table, used only the low three bits of each double’s bit pattern as its index: both low elements ended in 7 and became element 7.

AMD’s Zen 5 guide gives VPERMPD the figures of VPERMQ: a latency of 4 cycles, except for the index form on zmm registers, at 5.

In the optimization guide

What the optimization guide says about VPERMPD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Crestmont and Gracemont

• Vectors and AVX2: Shuffles that move data across the 128-bit halves are slower: VPERM2I128, VPERM2F128, VPERMD, VPERMQ, VPERMPS and VPERMPD on 256 bits are two micro-ops with a latency of 7 cycles, the second holding a port for two cycles.

Golden Cove and Raptor Cove

• Vectors, AVX-512 and AMX: VPERMD, VPERMQ, VPERMPS, VPERMPD, VPMULLQ, vrange, vgetmant and the half-precision complex multiplications wait for the old value of their destination, which they then overwrite.

Zen 2

• Vectors and floating point: AMD’s spreadsheet makes the AVX2 permutes that cross the 128-bit lanes, VPERMD, vpermps, vpermq and vpermpd, microcoded, while vperm2f128 is one macro-op of three cycles on pipe 2. sources differ

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    k = imm8 >> 2 * (i % 4) & 3
    j = i - i % 4 + k
    if k1[i]:  # 1 without a write mask
        zmm1.q[i] = src2.q[j]
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src2.f64[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

n = VL // 64  # 4 in ymm, 8 in zmm
for i in range(n):
    if k1[i]:
        zmm1.q[i] = src3.q[zmm2.q[i] % n]
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src3.f64[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPERMPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX2 instructions

• VPANDN
• VPAVGB
• VPAVGW
• VPBLENDD
• VPBLENDVB
• VPBLENDW
• VPBROADCASTB
• VPBROADCASTD
• VPBROADCASTQ
• VPBROADCASTW
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW
• VPCMPGTB
• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPERM2I128
• VPERMD
• VPERMPS
• VPERMQ
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPHADDD
• VPHADDSW
• VPHADDW
• VPHSUBD
• VPHSUBSW
• VPHSUBW
• VPMADDUBSW
• VPMADDWD
• VPMASKMOVD
• VPMASKMOVQ
• VPMAXSB
• VPMAXSD
• VPMAXSW
• VPMAXUB

All 138 AVX2 instructions

More AVX10.1 instructions

• VPCOMPRESSB
• VPCOMPRESSD
• VPCOMPRESSQ
• VPCOMPRESSW
• VPCONFLICTD
• VPCONFLICTQ
• VPDPBUSD
• VPDPBUSDS
• VPDPWSSD
• VPDPWSSDS
• VPERMB
• VPERMD
• VPERMI2B
• VPERMI2D
• VPERMI2PD
• VPERMI2PS
• VPERMI2Q
• VPERMI2W
• VPERMILPD
• VPERMILPS
• VPERMPS
• VPERMQ
• VPERMT2B
• VPERMT2D
• VPERMT2PD
• VPERMT2PS
• VPERMT2Q
• VPERMT2W
• VPERMW
• VPEXPANDB
• VPEXPANDD
• VPEXPANDQ
• VPEXPANDW
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD

All 686 AVX10.1 instructions