Instruction
VPERMPS
Rearranges singles across the whole register using an index vector.
- Extensions
- Forms
- 6 (2 VEX, 4 EVEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VPERMPS ymm, ymm, m256
VPERMPS_YMMqq_YMMqq_MEMqq | VEX.256.66.0F38.W0 16 /r | AVX2 |
VPERMPS ymm, ymm, ymm
VPERMPS_YMMqq_YMMqq_YMMqq | VEX.256.66.0F38.W0 16 /r | AVX2 |
VPERMPS zmm {k}{z}, zmm, zmm
VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 | EVEX.512.66.0F38.W0 16 /r | AVX10.1 or AVX512F |
VPERMPS zmm {k}{z}, zmm, m512/m32bcst
VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 | EVEX.512.66.0F38.W0 16 /r | AVX10.1 or AVX512F |
VPERMPS ymm {k}{z}, ymm, ymm
VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 | EVEX.256.66.0F38.W0 16 /r | AVX10.1 or AVX512F + AVX512VL |
VPERMPS ymm {k}{z}, ymm, m256/m32bcst
VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 | EVEX.256.66.0F38.W0 16 /r | AVX10.1 or AVX512F + AVX512VL |
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VPERMPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm256_permutevar8x32_ps
__m256 _mm256_permutevar8x32_ps(__m256 __a, __m256i __b) |
|
_mm256_permutexvar_ps
__m256 _mm256_permutexvar_ps(__m256i A, __m256 B) |
|
_mm256_mask_permutexvar_ps
__m256 _mm256_mask_permutexvar_ps(__m256 __W, __mmask8 __U, __m256i __X, __m256 __Y) |
|
_mm256_maskz_permutexvar_ps
__m256 _mm256_maskz_permutexvar_ps(__mmask8 __U, __m256i __X, __m256 __Y) |
|
_mm512_permutexvar_ps
__m512 _mm512_permutexvar_ps(__m512i __X, __m512 __Y) |
|
_mm512_mask_permutexvar_ps
__m512 _mm512_mask_permutexvar_ps(__m512 __W, __mmask16 __U, __m512i __X, __m512 __Y) |
|
_mm512_maskz_permutexvar_ps
__m512 _mm512_maskz_permutexvar_ps(__mmask16 __U, __m512i __X, __m512 __Y) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
More AVX10.1 instructions
- VPCOMPRESSD
- VPCOMPRESSQ
- VPCOMPRESSW
- VPCONFLICTD
- VPCONFLICTQ
- VPDPBUSD
- VPDPBUSDS
- VPDPWSSD
- VPDPWSSDS
- VPERMB
- VPERMD
- VPERMI2B
- VPERMI2D
- VPERMI2PD
- VPERMI2PS
- VPERMI2Q
- VPERMI2W
- VPERMILPD
- VPERMILPS
- VPERMPD
- VPERMQ
- VPERMT2B
- VPERMT2D
- VPERMT2PD
- VPERMT2PS
- VPERMT2Q
- VPERMT2W
- VPERMW
- VPEXPANDB
- VPEXPANDD
- VPEXPANDQ
- VPEXPANDW
- VPEXTRB
- VPEXTRD
- VPEXTRQ
- VPEXTRW
- VPGATHERDD
- VPGATHERDQ
- VPGATHERQD
- VPGATHERQQ
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.