x86-64.net

Instruction

VPERMPS

Rearranges singles across the whole register using an index vector.

Extensions
Forms
6 (2 VEX, 4 EVEX)
Data
Intel XED v2026.08.23

VPERMPS takes singles from anywhere in a vector: element i of the result is the element of the table that element i of the index vector numbers, using its low three bits for ymm registers and four for zmm. It is the single-precision twin of VPERMD, whose page covers the operand order (indices in the second operand, the table in the third, the other way round in the AVX2 intrinsic), left-packing and the two-table forms. The two give the same bits: the data are moved, not computed on, so no floating-point exception or MXCSR flag is possible. Like VPERMD it has no 128-bit form; within one xmm register, VPERMILPS does the job. The EVEX forms add masking and a broadcast single as the table.

Which one compilers pick

For float vectors, the choice between VPERMPS and VPERMD is the compiler’s. _mm256_permutevar8x32_ps becomes VPERMPS in GCC 14 and Clang 23 at -O2, but for shuffles written with __builtin_shufflevector on eight floats with -march=x86-64-v3 they part ways:

  • reversing the eight elements is VPERMPS with a constant index vector in Clang, and VPERMD in GCC;
  • repeating element 3 everywhere is a broadcast index and VPERMPS in Clang, and VPERMILPS within each lane followed by VPERM2F128 to copy the low lane up in GCC.

AMD’s Zen 5 guide lists VPERMPS and VPERMD alike: one macro-op with a latency of 4 cycles for ymm and 5 for zmm registers, so the choice costs nothing there. Shuffles that stay within 128-bit lanes are cheaper: VPERMILPS with an immediate has a latency of 1 cycle.

In the optimization guide

What the optimization guide says about VPERMPS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Crestmont and Gracemont

Golden Cove and Raptor Cove

Zen 2

  • Vectors and floating point: AMD’s spreadsheet makes the AVX2 permutes that cross the 128-bit lanes, VPERMD, vpermps, vpermq and vpermpd, microcoded, while vperm2f128 is one macro-op of three cycles on pipe 2. sources differ

Forms

Every encoding of VPERMPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPERMPS ymm, ymm, m256 VPERMPS_YMMqq_YMMqq_MEMqqVEX.256.66.0F38.W0 16 /rAVX2
VPERMPS ymm, ymm, ymm VPERMPS_YMMqq_YMMqq_YMMqqVEX.256.66.0F38.W0 16 /rAVX2
VPERMPS zmm {k}{z}, zmm, zmm VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512EVEX.512.66.0F38.W0 16 /rAVX10.1 or AVX512F
VPERMPS zmm {k}{z}, zmm, m512/m32bcst VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512EVEX.512.66.0F38.W0 16 /rAVX10.1 or AVX512F
VPERMPS ymm {k}{z}, ymm, ymm VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512EVEX.256.66.0F38.W0 16 /rAVX10.1 or AVX512F + AVX512VL
VPERMPS ymm {k}{z}, ymm, m256/m32bcst VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512EVEX.256.66.0F38.W0 16 /rAVX10.1 or AVX512F + AVX512VL

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelymm, ymm, m256ymm, ymm, ymmzmm {k}{z}, zmm, zmmzmm {k}{z}, zmm, m512/m32bcst
ymm {k}{z}, ymm, m256/m32bcst		ymm {k}{z}, ymm, ymm
Haswell, Skylake10 / 1p53 / 1p5
Broadwell9 / 1p53 / 1p5
Skylake-SP, Ice Lake10 / 1p53 / 1p53 / 1p510 / 1p53 / 1p5
Alder Lake11 / 1p53 / 1p5
Sapphire Rapids11 / 1p53 / 1p53 / 1p511 / 1p53 / 1p5
Lunar Lake11 / 0.5V2 V33 / 0.5V2 V3
Zen9 / 1FPU1 FPU22 / 1FPU1 FPU2
Zen 29 / 0.5FPU1 FPU22 / 0.5FPU1 FPU2
Zen 314 / 2FP17 / 1FP1
Zen 411 / 1FP14 / 1FP15 / 1FP1 FP214 / 1FP14 / 11FP1 FP2
  1. Zen 4 model: AMD's spreadsheets give reciprocal throughput 0.5 for Zen 4 and Zen 5 (AMD 57647, row 2286; AMD 58455, row 567).

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Permute by index: each single of the result is the single of the table zmm3 that the index in the same place of zmm2 numbers, across the whole register.
VPERMPS with an example index vectorWith the example indices, result singles 15 to 0: b8, unchanged (bit 14 of k1 is 0), b7, b10, b1, b5, b12, b5, b15, b2, b9, b6, b14, b0, b11, b3.0123567891011121314154zmm3or m512b1111111111111110k1b3b11b0b14b6b9b2b15b5b12b5b1b10b7b8zmm13110146921551251107138zmm2index

Example index vector in zmm2 (element 0 on the right); only its low 4 bits count. Shown for the zmm form; the ymm form works the same on 8 singles. The EVEX forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}.

With the example indices, result singles 15 to 0: b8, unchanged (bit 14 of k1 is 0), b7, b10, b1, b5, b12, b5, b15, b2, b9, b6, b14, b0, b11, b3.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

n = VL // 32   # 8 in ymm, 16 in zmm
for i in range(n):
    if k1[i]:  # 1 without a write mask
        zmm1.d[i] = src3.d[zmm2.d[i] % n]
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.f32[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 6 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPERMPS ymm, ymm, ymm/m256
ymmexplicitwrite
ymmexplicitread
ymm/m256explicitread
VPERMPS ymm {k}{z}, ymm, ymm/m256/m32bcst VPERMPS zmm {k}{z}, zmm, zmm/m512/m32bcst
ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
ymm, zmmexplicitread
ymm/m256/m32bcst, zmm/m512/m32bcstexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-4
EVEX forms
AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

EVEX forms
write masking
EVEX memory forms
embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPERMPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm256_permutevar8x32_ps __m256 _mm256_permutevar8x32_ps(__m256 __a, __m256i __b)

VPERMPS ymm, ymm, ymm VEX.256 -mavx2

_mm256_permutexvar_ps __m256 _mm256_permutexvar_ps(__m256i A, __m256 B)

VPERMPS ymm, ymm, ymm VEX.256 -mavx512vl

_mm256_mask_permutexvar_ps __m256 _mm256_mask_permutexvar_ps(__m256 __W, __mmask8 __U, __m256i __X, __m256 __Y)

VPERMPS ymm {k}, ymm, ymm EVEX.256 -mavx512vl

_mm256_maskz_permutexvar_ps __m256 _mm256_maskz_permutexvar_ps(__mmask8 __U, __m256i __X, __m256 __Y)

VPERMPS ymm {k}{z}, ymm, ymm EVEX.256 -mavx512vl

_mm512_permutexvar_ps __m512 _mm512_permutexvar_ps(__m512i __X, __m512 __Y)

VPERMPS zmm, zmm, zmm EVEX.512 -mavx512f

_mm512_mask_permutexvar_ps __m512 _mm512_mask_permutexvar_ps(__m512 __W, __mmask16 __U, __m512i __X, __m512 __Y)

VPERMPS zmm {k}, zmm, zmm EVEX.512 -mavx512f

_mm512_maskz_permutexvar_ps __m512 _mm512_maskz_permutexvar_ps(__mmask16 __U, __m512i __X, __m512 __Y)

VPERMPS zmm {k}{z}, zmm, zmm EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6
AVX512F_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6

More AVX2 instructions

All 138 AVX2 instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2C, page 5-526 (VPERMPS)
  6. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  7. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.