VPERMQ

VPERMQ rearranges the quadwords of a vector freely, across the 128-bit lanes that most AVX2 shuffles cannot cross. AVX2 gave it one form: an immediate with two bits per result element, each naming one of the four quadwords of a YMM register or of memory, so that any arrangement, repeats included, is one instruction. Common values:

• 0xD8 (elements 0, 2, 1, 3) restores the order after an in-lane pack such as VPACKUSWB; GCC 14 at -O2 narrows 16-bit elements to bytes that way, while Clang 23 packs the two halves of each register in XMM registers instead.
• 0x1B reverses the four quadwords: GCC compiles a loop that copies an array of 64-bit integers backwards to VPERMQ with a memory source.
• 0x4E swaps the two halves, as VPERM2I128 can.
• 0x08 and 0x0D gather the even and the odd elements into the low half; Intel’s optimization guide suggests them, after one load, in place of a gather for a small stride (Section 15.16.4).

Immediate or index vector#

AVX-512 added a form that takes the selectors from a vector register, as VPERMD does for doublewords, with masking and broadcast; only the low three bits of each index count in a ZMM register and the low two in a YMM one. The immediate form also has a ZMM version, but there it is not a permutation of eight elements: it applies the same four selectors to each 256-bit half separately, as the page’s pseudocode shows. Use the index form, or VPERMT2Q for two tables, to move quadwords between the halves.

VPERMPD is the same instruction for doubles, and Clang 23 picks between the two by the instructions around them: _mm256_permute4x64_epi64 on its own compiles to VPERMPD, and followed by an integer addition to VPERMQ. GCC 14 keeps VPERMQ.

Intel’s guide lists VPERMQ, with VPERMD, VPERMPS and VPERMPD, among the instructions that falsely depend on their destination register in the Golden Cove microarchitecture, and recommends a zero idiom on the destination before them (Section 2.4.1.2). In Crestmont they take two micro-ops and a seven-cycle latency (Section 4.1.9.1).

In the optimization guide

What the optimization guide says about VPERMQ, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Crestmont and Gracemont

• Vectors and AVX2: Shuffles that move data across the 128-bit halves are slower: VPERM2I128, VPERM2F128, VPERMD, VPERMQ, VPERMPS and VPERMPD on 256 bits are two micro-ops with a latency of 7 cycles, the second holding a port for two cycles.

Golden Cove and Raptor Cove

• Vectors, AVX-512 and AMX: VPERMD, VPERMQ, VPERMPS, VPERMPD, VPMULLQ, vrange, vgetmant and the half-precision complex multiplications wait for the old value of their destination, which they then overwrite.

Zen 2

• Vectors and floating point: AMD’s spreadsheet makes the AVX2 permutes that cross the 128-bit lanes, VPERMD, vpermps, vpermq and vpermpd, microcoded, while vperm2f128 is one macro-op of three cycles on pipe 2. sources differ

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    k = imm8 >> 2 * (i % 4) & 3
    j = i - i % 4 + k
    if k1[i]:  # 1 without a write mask
        zmm1.q[i] = src2.q[j]
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src2.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

n = VL // 64  # 4 in ymm, 8 in zmm
for i in range(n):
    if k1[i]:
        zmm1.q[i] = src3.q[zmm2.q[i] % n]
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src3.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPERMQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX2 instructions

• VPAVGW
• VPBLENDD
• VPBLENDVB
• VPBLENDW
• VPBROADCASTB
• VPBROADCASTD
• VPBROADCASTQ
• VPBROADCASTW
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW
• VPCMPGTB
• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPERM2I128
• VPERMD
• VPERMPD
• VPERMPS
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPHADDD
• VPHADDSW
• VPHADDW
• VPHSUBD
• VPHSUBSW
• VPHSUBW
• VPMADDUBSW
• VPMADDWD
• VPMASKMOVD
• VPMASKMOVQ
• VPMAXSB
• VPMAXSD
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUW

All 138 AVX2 instructions

More AVX10.1 instructions

• VPCOMPRESSQ
• VPCOMPRESSW
• VPCONFLICTD
• VPCONFLICTQ
• VPDPBUSD
• VPDPBUSDS
• VPDPWSSD
• VPDPWSSDS
• VPERMB
• VPERMD
• VPERMI2B
• VPERMI2D
• VPERMI2PD
• VPERMI2PS
• VPERMI2Q
• VPERMI2W
• VPERMILPD
• VPERMILPS
• VPERMPD
• VPERMPS
• VPERMT2B
• VPERMT2D
• VPERMT2PD
• VPERMT2PS
• VPERMT2Q
• VPERMT2W
• VPERMW
• VPEXPANDB
• VPEXPANDD
• VPEXPANDQ
• VPEXPANDW
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPINSRB

All 686 AVX10.1 instructions