VPERMT2B

VPERMT2B fills each byte of its destination from a table of two registers, the destination itself and the third operand, at the index held in the matching byte of the second operand. It is the byte member of the two-table permutes that VPERMT2D and VPERMI2D explain: the T form overwrites the first table and keeps the indices, VPERMI2B overwrites the indices. It came with AVX512_VBMI, together with VPERMB, which looks up one register.

A table of 128 bytes#

With 64 bytes per zmm register, the two registers hold 128 entries: bits 5:0 of an index pick the byte and bit 6 the register, and bit 7 is ignored, so every byte value is a valid index and needs no masking. In the ymm and xmm forms the table shrinks to 64 and 32 bytes, with 6 and 5 index bits. A 128-entry table covers 7-bit ASCII, so one instruction can map 64 characters at once, for example to classes or to another case. Intel’s optimization manual looks up 64 input bytes per VPERMI2B in such a table, out[i] = table[in[i] & 127], and reports it 5.3 times as fast as an AVX512BW version that widens the bytes to words for VPERMI2W (Section 17.17.2, Example 17-27).

In compiled code#

GCC 14 and Clang 23 at -O2 need VBMI enabled (-mavx512vbmi, or a -march such as znver4, znver5 or icelake-server; x86-64-v4 lacks it). With -march=znver5, a constant shuffle taking the even bytes of two zmm registers is one two-table permute: Clang emits VPERMT2B, GCC VPERMI2B. Clang also vectorizes the split of interleaved bytes, l[i] = s[2*i]; r[i] = s[2*i+1];, with VPERMT2B. Neither compiler turned the manual’s lookup loop into a permute: both kept it scalar. For the intrinsic _mm512_permutex2var_epi8(a, idx, b) both emit VPERMT2B over a; the merging _mm512_mask_permutex2var_epi8 is VPERMT2B and _mm512_mask2_permutex2var_epi8 VPERMI2B.

AMD’s Zen 5 guide lists VPERMT2B as one macro-op with a latency of 3, 4 and 5 cycles for xmm, ymm and zmm, the same as VPERMB for zmm: the second table register costs nothing extra.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

n = VL // 8         # 16 in xmm, 32 in ymm, 64 in zmm
src1 = zmm1.read()  # the first table: zmm1 as it was
for i in range(n):
    if k1[i]:
        x = zmm2.b[i]
        if x & n:
            zmm1.b[i] = src3.b[x % n]
        else:
            zmm1.b[i] = src1.b[x % n]
    elif zeroing:
        zmm1.b[i] = 0
    # else: zmm1.b[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPERMT2B, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPCOMPRESSW
• VPCONFLICTD
• VPCONFLICTQ
• VPDPBUSD
• VPDPBUSDS
• VPDPWSSD
• VPDPWSSDS
• VPERMB
• VPERMD
• VPERMI2B
• VPERMI2D
• VPERMI2PD
• VPERMI2PS
• VPERMI2Q
• VPERMI2W
• VPERMILPD
• VPERMILPS
• VPERMPD
• VPERMPS
• VPERMQ
• VPERMT2D
• VPERMT2PD
• VPERMT2PS
• VPERMT2Q
• VPERMT2W
• VPERMW
• VPEXPANDB
• VPEXPANDD
• VPEXPANDQ
• VPEXPANDW
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPINSRB
• VPINSRD

All 686 AVX10.1 instructions