VPERMT2D

VPERMT2D fills each doubleword of its destination from a table of two registers, the destination itself (elements 0 to 15 of a ZMM table) and the third operand (16 to 31), at the index held in the matching element of the second operand. Index bits and table sizes are those of VPERMI2D, whose page explains the pair; the difference is which register the result replaces. VPERMT2D overwrites the first half of the table and keeps the indices, which suits a constant index vector used again on every iteration of a loop.

Merging into the table#

Under a merge mask, the elements left out keep the first table’s values, so a masked VPERMT2D replaces chosen elements of a register with any elements of it and one other register. _mm512_mask_permutex2var_epi32(a, k, idx, b) stands for that form, and _mm512_maskz_permutex2var_epi32 for the zeroing one; GCC 14 and Clang 23 at -O2 compile both to a single VPERMT2D.

Any two-register shuffle#

Most of AVX-512’s fixed shuffles, such as VPUNPCKLDQ and VPSHUFD, work inside 128-bit lanes. A constant pattern that crosses lanes and takes from two registers, such as interleaving the low halves of a and b (__builtin_shufflevector(a, b, 0, 16, 1, 17, ...)), costs one index load and one two-table permute: Clang 23 with -march=x86-64-v4 emits VPERMT2D over a, GCC 14 VPERMI2D over the loaded index after copying a. A pattern drawn from one register gets the one-table VPERMD instead.

Interleaving two arrays into pairs is the store side of the deinterleave that the VPERMI2D page shows. Intel’s optimization manual does it with VPERMI2D and VPERMT2D before ordinary stores in place of two scatters, 4.4 times as fast (Section 17.22.2, Example 17-32); GCC 14 vectorizes c[2*i] = re[i]; c[2*i+1] = im[i]; at -march=x86-64-v4 with two VPERMT2Ds per 32 results.

AMD’s Zen 5 guide lists VPERMT2D as one macro-op with a latency of 3, 4 and 5 cycles for XMM, YMM and ZMM, the same as VPERMI2D and, for ZMM, as VPERMD: the second table register costs nothing extra. VPERMT2Q, VPERMT2PS, VPERMT2W and VPERMT2B do the same for other elements.

In the optimization guide

What the optimization guide says about VPERMT2D, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Vectors

• Shuffles and lane crossing: AVX-512’s two-source permutes and VBMI’s VPERMB take any element of their sources, each in one macro-op on Zen 5.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

n = VL // 32        # 4 in xmm, 8 in ymm, 16 in zmm
src1 = zmm1.read()  # the first table: zmm1 as it was
for i in range(n):
    if k1[i]:
        x = zmm2.d[i]
        if x & n:
            zmm1.d[i] = src3.d[x % n]
        else:
            zmm1.d[i] = src1.d[x % n]
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPERMT2D, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPCONFLICTD
• VPCONFLICTQ
• VPDPBUSD
• VPDPBUSDS
• VPDPWSSD
• VPDPWSSDS
• VPERMB
• VPERMD
• VPERMI2B
• VPERMI2D
• VPERMI2PD
• VPERMI2PS
• VPERMI2Q
• VPERMI2W
• VPERMILPD
• VPERMILPS
• VPERMPD
• VPERMPS
• VPERMQ
• VPERMT2B
• VPERMT2PD
• VPERMT2PS
• VPERMT2Q
• VPERMT2W
• VPERMW
• VPEXPANDB
• VPEXPANDD
• VPEXPANDQ
• VPEXPANDW
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPINSRB
• VPINSRD
• VPINSRQ

All 686 AVX10.1 instructions