VPERMT2PD

VPERMT2PD fills each double of its destination from a table of two registers, the destination itself and the third operand, at the index in the matching quadword of the second operand. It moves the same bits as VPERMT2Q, whose page gives the index bits: 2:0 for the element and 3 for the register at 512 bits. VPERMI2PD is the twin that overwrites the indices instead, and VPERMI2D explains the pair. The doubles are moved as bit patterns: in its 6 recorded cases on Zen 5, MXCSR stayed 1F80h.

Recorded on Zen 5#

• Indices read first. vpermt2pd zmm9{k4}, zmm9, zmm14 used ZMM9 as indices and first table at once. Its element 0 held an index ending in 0010b and element 2 one ending in 0000b, and the two elements swapped their old values; elements 6 and 7, with bit 3 set, came from ZMM14.
• Merging keeps the table. In vpermt2pd zmm1{k7}, zmm2, qword bcst [mem], elements 2 to 4, left out by E3h, kept the values ZMM1 held as the table, where a merging VPERMI2PD keeps the indices. Elements 6 and 7 had bit 3 set and took the broadcast double.

In compiled code#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 compile _mm512_permutex2var_pd and _mm512_mask_permutex2var_pd, whose mask falls back to the table, to VPERMT2PD. Interleaving two double arrays into one, c[2*i] = re[i]; c[2*i+1] = im[i];, takes two VPERMT2PDs and a register copy per pair of vectors, on ZMM registers in GCC and on YMM registers in Clang. The reverse split is VPERMT2PD in GCC too, while Clang uses VPERM2F128 with VUNPCKLPD and VUNPCKHPD. For a fixed shuffle of two vectors, such as their odd elements with __builtin_shufflevector, Clang emits VPERMT2PD over the first and GCC VPERMI2PD over the loaded indices.

AMD’s Zen 5 latency spreadsheet gives VPERMT2PD 3, 4 and 5 cycles for XMM, YMM and ZMM registers, two per cycle on pipes FP1 and FP2, as for VPERMI2PD. Zen 5’s 6 recorded cases cover the register, memory and broadcast forms at all three widths.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

n = VL // 64        # 2 in xmm, 4 in ymm, 8 in zmm
src1 = zmm1.read()  # the first table: zmm1 as it was
for i in range(n):
    if k1[i]:
        x = zmm2.q[i]
        if x & n:
            zmm1.q[i] = src3.q[x % n]
        else:
            zmm1.q[i] = src1.q[x % n]
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src3.f64[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPERMT2PD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPCONFLICTQ
• VPDPBUSD
• VPDPBUSDS
• VPDPWSSD
• VPDPWSSDS
• VPERMB
• VPERMD
• VPERMI2B
• VPERMI2D
• VPERMI2PD
• VPERMI2PS
• VPERMI2Q
• VPERMI2W
• VPERMILPD
• VPERMILPS
• VPERMPD
• VPERMPS
• VPERMQ
• VPERMT2B
• VPERMT2D
• VPERMT2PS
• VPERMT2Q
• VPERMT2W
• VPERMW
• VPEXPANDB
• VPEXPANDD
• VPEXPANDQ
• VPEXPANDW
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPINSRB
• VPINSRD
• VPINSRQ
• VPINSRW

All 686 AVX10.1 instructions