VPERMT2PS

VPERMT2PS fills each single of its destination from a table of two registers, the destination itself and the third operand, at the index in the matching doubleword of the second operand. It is the T form of VPERMI2PS, whose page explains the index bits for singles, four for the element and one for the register at 512 bits, and why MXCSR plays no part; VPERMI2D explains the I and T pair. VPERMT2D moves the same bits.

Recorded on Zen 5#

• Broadcast table. In vpermt2ps zmm24{k7}, zmm3, dword bcst [mem] the second table was one single repeated. Of the 10 elements that F2E3h selects, the 6 whose index had bit 4 set took that single and the other 4 picked elements of ZMM24, read before any was written; the 6 unselected elements kept their table values.
• Bits 1:0 and 2 at 128 bits. vpermt2ps xmm24, xmm3, xmm3 used XMM3 as indices and second table. Its indices ended in 111b, 011b, 111b and 011b, so the result alternated element 3 of XMM3 with element 3 of XMM24, and the bits from 128 up were cleared.

In compiled code#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 compile _mm512_permutex2var_ps and its merging form to VPERMT2PS. Splitting interleaved float pairs into two arrays, re[i] = c[2*i]; im[i] = c[2*i+1];, takes two VPERMT2PSs and a register copy per pair of vectors in both, on ZMM registers in GCC and on YMM registers in Clang. For the opposite interleave GCC does the same; Clang loads four singles of the first array spread to every other doubleword with VPMOVZXDQ, so that VPERMT2PS only has to fill the gaps from the second array. For a fixed shuffle of two vectors, such as their odd elements, Clang emits VPERMT2PS and GCC VPERMI2PS over the loaded indices.

AMD’s Zen 5 latency spreadsheet gives VPERMT2PS 3, 4 and 5 cycles for XMM, YMM and ZMM registers, two per cycle on pipes FP1 and FP2. Zen 5’s 6 recorded cases cover the register, memory and broadcast forms at all three widths, with MXCSR at 1F80h before and after.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

n = VL // 32        # 4 in xmm, 8 in ymm, 16 in zmm
src1 = zmm1.read()  # the first table: zmm1 as it was
for i in range(n):
    if k1[i]:
        x = zmm2.d[i]
        if x & n:
            zmm1.d[i] = src3.d[x % n]
        else:
            zmm1.d[i] = src1.d[x % n]
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.f32[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPERMT2PS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPDPBUSD
• VPDPBUSDS
• VPDPWSSD
• VPDPWSSDS
• VPERMB
• VPERMD
• VPERMI2B
• VPERMI2D
• VPERMI2PD
• VPERMI2PS
• VPERMI2Q
• VPERMI2W
• VPERMILPD
• VPERMILPS
• VPERMPD
• VPERMPS
• VPERMQ
• VPERMT2B
• VPERMT2D
• VPERMT2PD
• VPERMT2Q
• VPERMT2W
• VPERMW
• VPEXPANDB
• VPEXPANDD
• VPEXPANDQ
• VPEXPANDW
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPINSRB
• VPINSRD
• VPINSRQ
• VPINSRW
• VPLZCNTD

All 686 AVX10.1 instructions