VPERMT2Q

VPERMT2Q fills each quadword of its destination from a table of two registers, the destination itself and the third operand, at the index held in the matching quadword of the second operand. It is the quadword form of VPERMT2D, and VPERMI2Q is its twin that overwrites the indices instead of the table; VPERMI2D explains the pair and the intrinsics that stand for both.

Index bits#

With 8 quadwords to a ZMM register, the table holds 16 elements: bits 2:0 of each index choose the element and bit 3 the register, and the other 60 bits are ignored. YMM and XMM tables hold 8 and 4 elements and use bits 2:0 and 1:0. The cases recorded on Zen 5 used random 64-bit indices: 65F2A504C4AFBE7Eh, whose low four bits are 1110b, picked element 6 of the second register, and F60E43C7B5D831E7h element 7 of the first. Nothing forbids one register in two roles: vpermt2q xmm9, xmm9, xmm14 used XMM9 as indices and first table at once, and its element 0, whose index ended in 00b, came back unchanged.

In compiled code#

Interleaving two int64_t arrays, c[2*i] = re[i]; c[2*i+1] = im[i];, and the reverse split both take two VPERMT2Qs per pair of registers in GCC 14 and Clang 23 at -O2 with -march=x86-64-v4, one with the indices of the low or even halves and one with those of the high or odd ones; GCC works on ZMM and Clang on YMM registers. As each permute overwrites a table, one of the two first copies its register. For a fixed shuffle of two arguments, __builtin_shufflevector(a, b, 0, 8, 1, 9, ...), Clang emits VPERMT2Q over a and GCC VPERMI2Q over the loaded indices. VPERMT2PD does the same for doubles.

AMD’s latency spreadsheet for Zen 5 lists VPERMT2Q as VPERMT2D: one macro-op with a latency of 3, 4 and 5 cycles for XMM, YMM and ZMM.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

n = VL // 64        # 2 in xmm, 4 in ymm, 8 in zmm
src1 = zmm1.read()  # the first table: zmm1 as it was
for i in range(n):
    if k1[i]:
        x = zmm2.q[i]
        if x & n:
            zmm1.q[i] = src3.q[x % n]
        else:
            zmm1.q[i] = src1.q[x % n]
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src3.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPERMT2Q, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPDPBUSDS
• VPDPWSSD
• VPDPWSSDS
• VPERMB
• VPERMD
• VPERMI2B
• VPERMI2D
• VPERMI2PD
• VPERMI2PS
• VPERMI2Q
• VPERMI2W
• VPERMILPD
• VPERMILPS
• VPERMPD
• VPERMPS
• VPERMQ
• VPERMT2B
• VPERMT2D
• VPERMT2PD
• VPERMT2PS
• VPERMT2W
• VPERMW
• VPEXPANDB
• VPEXPANDD
• VPEXPANDQ
• VPEXPANDW
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPINSRB
• VPINSRD
• VPINSRQ
• VPINSRW
• VPLZCNTD
• VPLZCNTQ

All 686 AVX10.1 instructions