VPERMT2W

VPERMT2W fills each word of its destination from a table of two registers, the destination itself and the third operand, at the index held in the matching word of the second operand. It is the word form of VPERMT2D, which explains why the T form keeps its indices and overwrites the table, and VPERMI2W is the twin that overwrites the indices. It needs AVX512BW, where VPERMT2B needs AVX512_VBMI, and has no broadcast form.

Index bits#

A ZMM table holds 64 words, so bits 5:0 of each index count, bit 5 choosing the register; YMM and XMM tables use bits 4:0 and 3:0, and the higher bits are ignored. In the recorded Zen 5 case vpermt2w xmm14, xmm8, xmm29, index BD34h picked word 4 of XMM14, D661h word 1, 8638h word 0 of XMM29 and E19Ah word 2 of XMM29; the register above the eight words was cleared. In vpermt2w zmm5{k5}, zmm5, zmm5, where one register is index and both tables, every index was read before any element was written.

In compiled code#

Taking the even and the odd words apart, ev[i] = s[2*i] and od[i] = s[2*i+1] over int16_t arrays, is one VPERMT2W per output vector in GCC 14 and Clang 23 at -O2 with -march=x86-64-v4, with the index vectors 0, 2, 4 … and 1, 3, 5 … loaded once before the loop: GCC on ZMM and Clang on YMM registers, each copying the first table first because the permute overwrites it. GCC narrows doublewords to words the same way, a VPERMT2W of two loads picking the low halves, where Clang uses VPMOVDW. _mm512_permutex2var_epi16 and its _mask_ form are VPERMT2W in GCC; the _mask2_ form, which merges into the indices, is VPERMI2W.

AMD’s Zen 5 latency spreadsheet gives VPERMT2W one macro-op on FP1 or FP2, with 3, 4 and 5 cycles of latency for XMM, YMM and ZMM, as VPERMT2B.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

n = VL // 16        # 8 in xmm, 16 in ymm, 32 in zmm
src1 = zmm1.read()  # the first table: zmm1 as it was
for i in range(n):
    if k1[i]:
        x = zmm2.w[i]
        if x & n:
            zmm1.w[i] = src3.w[x % n]
        else:
            zmm1.w[i] = src1.w[x % n]
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPERMT2W, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPDPWSSD
• VPDPWSSDS
• VPERMB
• VPERMD
• VPERMI2B
• VPERMI2D
• VPERMI2PD
• VPERMI2PS
• VPERMI2Q
• VPERMI2W
• VPERMILPD
• VPERMILPS
• VPERMPD
• VPERMPS
• VPERMQ
• VPERMT2B
• VPERMT2D
• VPERMT2PD
• VPERMT2PS
• VPERMT2Q
• VPERMW
• VPEXPANDB
• VPEXPANDD
• VPEXPANDQ
• VPEXPANDW
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPINSRB
• VPINSRD
• VPINSRQ
• VPINSRW
• VPLZCNTD
• VPLZCNTQ
• VPMADD52HUQ

All 686 AVX10.1 instructions