VPERMW

VPERMW builds each word of its result by picking a word of a table: the index word in the same position of the first source says which word of the second source to take, anywhere in the register. It came with AVX512BW and has no VEX form. Before it, no single instruction moved 16-bit elements across the 128-bit lanes of a vector: AVX2 code combines VPSHUFB, which picks bytes within each lane, with a lane move such as VPERMQ. Intel’s optimization manual lists VPERMW among AVX-512’s new shuffles, the one-table permute beside the two-table VPERMI2W and VPERMT2W (Section 17.8).

Indices and operand order#

Only the low 3, 4 or 5 bits of an index count, for the 8, 16 or 32 words of the xmm, ymm and zmm forms; the bits above are ignored, so no index gives a zero word, and zeros come from a write mask with {z} instead. In a case recorded on Zen 5 with the xmm form, the index 7239h took word 1 of the table and E22Bh word 3. As in VPERMB and VPERMD, the indices are the first source, always a register, and the table is the operand that may be in memory, as the intrinsic _mm512_permutexvar_epi16(idx, table) orders them. Unlike VPERMD, VPERMW has no embedded broadcast: the memory operand is always a whole vector.

Where it appears#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 compile a reversal of the 32 words of a 512-bit vector, written with __builtin_shufflevector, to one VPERMW with the indices loaded from memory. The same reversal of the 8 words of an xmm register stays a VPSHUFB, which reaches every byte of a single lane.

Words are also the size of FP16 and BF16 numbers, and a permute only moves bits: Clang’s _mm512_permutexvar_ph (AVX512-FP16) and _mm512_permutexvar_pbh (AVX10.2) compile to VPERMW as well.

AMD’s Zen 5 guide lists VPERMW as one macro-op with a latency of 2, 4 and 5 cycles for the xmm, ymm and zmm forms, the same as VPERMB.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

n = VL // 16  # 8 in xmm, 16 in ymm, 32 in zmm
for i in range(n):
    if k1[i]:
        zmm1.w[i] = src3.w[zmm2.w[i] % n]
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPERMW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPDPWSSDS
• VPERMB
• VPERMD
• VPERMI2B
• VPERMI2D
• VPERMI2PD
• VPERMI2PS
• VPERMI2Q
• VPERMI2W
• VPERMILPD
• VPERMILPS
• VPERMPD
• VPERMPS
• VPERMQ
• VPERMT2B
• VPERMT2D
• VPERMT2PD
• VPERMT2PS
• VPERMT2Q
• VPERMT2W
• VPEXPANDB
• VPEXPANDD
• VPEXPANDQ
• VPEXPANDW
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPINSRB
• VPINSRD
• VPINSRQ
• VPINSRW
• VPLZCNTD
• VPLZCNTQ
• VPMADD52HUQ
• VPMADD52LUQ

All 686 AVX10.1 instructions