x86-64.net

Instruction

VPERMW

Rearranges the words of a vector across the whole register using an index vector.

Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VPERMW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPERMW xmm {k}{z}, xmm, xmm VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512EVEX.128.66.0F38.W1 8D /rAVX10.1 or AVX512BW + AVX512VL
VPERMW xmm {k}{z}, xmm, m128 VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512EVEX.128.66.0F38.W1 8D /rAVX10.1 or AVX512BW + AVX512VL
VPERMW ymm {k}{z}, ymm, ymm VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512EVEX.256.66.0F38.W1 8D /rAVX10.1 or AVX512BW + AVX512VL
VPERMW ymm {k}{z}, ymm, m256 VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512EVEX.256.66.0F38.W1 8D /rAVX10.1 or AVX512BW + AVX512VL
VPERMW zmm {k}{z}, zmm, zmm VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512EVEX.512.66.0F38.W1 8D /rAVX10.1 or AVX512BW
VPERMW zmm {k}{z}, zmm, m512 VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512EVEX.512.66.0F38.W1 8D /rAVX10.1 or AVX512BW

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPERMW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_permutexvar_epi16 __m128i _mm_permutexvar_epi16(__m128i __A, __m128i __B)

VPERMW xmm, xmm, xmm EVEX.128 -mavx512vl -mavx512bw

_mm_permutexvar_pbh __m128bh _mm_permutexvar_pbh(__m128i __A, __m128bh __B)

VPERMW xmm, xmm, xmm EVEX.128 -mavx10.2

_mm_permutexvar_ph __m128h _mm_permutexvar_ph(__m128i __A, __m128h __B)

VPERMW xmm, xmm, xmm EVEX.128 -mavx512fp16 -mavx512vl

_mm_mask_permutexvar_epi16 __m128i _mm_mask_permutexvar_epi16(__m128i __W, __mmask8 __M, __m128i __A, __m128i __B)

VPERMW xmm {k}, xmm, xmm EVEX.128 -mavx512vl -mavx512bw

_mm_maskz_permutexvar_epi16 __m128i _mm_maskz_permutexvar_epi16(__mmask8 __M, __m128i __A, __m128i __B)

VPERMW xmm {k}{z}, xmm, xmm EVEX.128 -mavx512vl -mavx512bw

_mm256_permutexvar_epi16 __m256i _mm256_permutexvar_epi16(__m256i __A, __m256i __B)

VPERMW ymm, ymm, ymm EVEX.256 -mavx512vl -mavx512bw

_mm256_permutexvar_pbh __m256bh _mm256_permutexvar_pbh(__m256i __A, __m256bh __B)

VPERMW ymm, ymm, ymm EVEX.256 -mavx10.2

_mm256_permutexvar_ph __m256h _mm256_permutexvar_ph(__m256i __A, __m256h __B)

VPERMW ymm, ymm, ymm EVEX.256 -mavx512fp16 -mavx512vl

_mm256_mask_permutexvar_epi16 __m256i _mm256_mask_permutexvar_epi16(__m256i __W, __mmask16 __M, __m256i __A, __m256i __B)

VPERMW ymm {k}, ymm, ymm EVEX.256 -mavx512vl -mavx512bw

_mm256_maskz_permutexvar_epi16 __m256i _mm256_maskz_permutexvar_epi16(__mmask16 __M, __m256i __A, __m256i __B)

VPERMW ymm {k}{z}, ymm, ymm EVEX.256 -mavx512vl -mavx512bw

_mm512_permutexvar_epi16 __m512i _mm512_permutexvar_epi16(__m512i __A, __m512i __B)

VPERMW zmm, zmm, zmm EVEX.512 -mavx512bw

_mm512_permutexvar_pbh __m512bh _mm512_permutexvar_pbh(__m512i __A, __m512bh __B)

VPERMW zmm, zmm, zmm EVEX.512 -mavx10.2

_mm512_permutexvar_ph __m512h _mm512_permutexvar_ph(__m512i __A, __m512h __B)

VPERMW zmm, zmm, zmm EVEX.512 -mavx512fp16

_mm512_mask_permutexvar_epi16 __m512i _mm512_mask_permutexvar_epi16(__m512i __W, __mmask32 __M, __m512i __A, __m512i __B)

VPERMW zmm {k}, zmm, zmm EVEX.512 -mavx512bw

_mm512_maskz_permutexvar_epi16 __m512i _mm512_maskz_permutexvar_epi16(__mmask32 __M, __m512i __A, __m512i __B)

VPERMW zmm {k}{z}, zmm, zmm EVEX.512 -mavx512bw

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512BW_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512BW_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512BW_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.