VPEXPANDB

VPEXPANDB takes consecutive bytes from the low end of its source and places them, in order, at the destination bytes whose mask bits are set; the other bytes keep their values, or become zero with {z}. It is the byte form of VPEXPANDD, whose page explains the operation and the unpacking loop around it, and the reverse of VPCOMPRESSB. AVX512_VBMI2 added it together with VPEXPANDW for words; before that, AVX-512 expanded only doublewords and quadwords.

A mask bit per byte#

A zmm register holds 64 bytes, so the mask is all 64 bits of a mask register, loaded with KMOVQ, and the number of bytes consumed is POPCNT of it on 64 bits. From memory, only that many bytes are read, so a load ending at a buffer’s end cannot fault on the next page. Its 8-bit displacement counts single bytes. In a case recorded on Zen 5, the xmm form with {z} and a mask of F2C9h, nine bits set, read nine bytes from memory, put them at bytes 0, 3, 6, 7, 9 and 12 to 15, and zeroed the other seven.

Decompressing sparse data#

Intel’s optimization manual stores the weights of a sparse neural network as the nonzero bytes and one bit per byte saying which bytes they were, built offline with VPTESTMB and VPCOMPRESSB. Before AMX multiplies the matrix, each row of 64 bytes is rebuilt with a zeroing VPEXPANDB under its 64-bit mask, and the input pointer advances by the mask’s population count (Section 20.18, Example 20-31). The manual loads 64 bytes and expands the register; GCC 14 and Clang 23 at -O2 with -mavx512vbmi2 fold that load into the memory form, so the compiled loop of KMOVQ, VPEXPANDB, POPCNT and a store reads only the bytes it uses.

The compilers emit VPEXPANDB only from its intrinsics, and only with VBMI2 enabled (-mavx512vbmi2, or a -march such as icelake-server or znver4; x86-64-v4 lacks it). Neither vectorized a scalar loop of the form d[i] = keep[i] ? c[j++] : 0, even at -O3 for znver5, and a constant shuffle that spreads bytes among zeros became a VPSHUFB.

AMD’s Zen 5 guide lists VPEXPANDB like VPEXPANDD, two macro-ops with a latency of 2, 4 and 5 cycles for xmm, ymm and zmm, for a register or memory source alike; only the compresses to memory are microcoded.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

j = 0
for i in range(VL // 8):
    if k1[i]:
        zmm1.b[i] = src2.b[j]
        j += 1
    elif zeroing:
        zmm1.b[i] = 0
    # else: zmm1.b[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPEXPANDB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPERMB
• VPERMD
• VPERMI2B
• VPERMI2D
• VPERMI2PD
• VPERMI2PS
• VPERMI2Q
• VPERMI2W
• VPERMILPD
• VPERMILPS
• VPERMPD
• VPERMPS
• VPERMQ
• VPERMT2B
• VPERMT2D
• VPERMT2PD
• VPERMT2PS
• VPERMT2Q
• VPERMT2W
• VPERMW
• VPEXPANDD
• VPEXPANDQ
• VPEXPANDW
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPINSRB
• VPINSRD
• VPINSRQ
• VPINSRW
• VPLZCNTD
• VPLZCNTQ
• VPMADD52HUQ
• VPMADD52LUQ
• VPMADDUBSW

All 686 AVX10.1 instructions