VPEXPANDD

VPEXPANDD is the reverse of VPCOMPRESSD: it takes consecutive doublewords from the low end of its source and spreads them, in order, over the destination elements whose mask bits are set. With mask bits 1, 2 and 5 set, elements 0, 1 and 2 of the source land in elements 1, 2 and 5. The other elements keep their old values, or become zero with {z}. Without a mask it is a plain copy.

The memory form#

From memory, VPEXPANDD reads only as many elements as the mask has set bits, one after another from the address, and nothing above them. A read that stops at the end of a buffer cannot fault on the page beyond, so a loop can take the next few values from a packed stream without padding it. The 8-bit displacement of this form counts in elements of 4 bytes, not in whole vectors as for most EVEX loads, which matters only to someone encoding it by hand.

Unpacking a stream#

The usual pattern is a mask from a compare, an unaligned load at a running position in the packed data, VPEXPANDD, and POPCNT of the mask, moved over with KMOVW or KMOVD, to advance the position. Intel’s optimization manual times it on a loop that gives each positive element the next value from the array (Section 17.6.1, Example 17-14): VPEXPANDD runs 8.58 times as fast as scalar code, against 4.23 for AVX2, which needs a table of 256 VPERMD index vectors and a VMASKMOVPS store. The same manual expands sparse matrices for AMX with the byte form, VPEXPANDB, one 64-bit mask per row (Section 20.18, Example 20-31).

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 emit VPEXPANDD for the intrinsics, _mm512_maskz_expand_epi32 for the register form and _mm512_maskz_expandloadu_epi32 for the memory form, each with a merging mask variant, but neither vectorizes the manual’s loop: both keep it scalar.

AMD’s Zen 5 guide lists VPEXPANDD as two macro-ops with a latency of 2, 4 and 5 cycles for XMM, YMM and ZMM, from a register or memory alike, while it marks the memory form of VPCOMPRESSD as microcoded. VPEXPANDQ expands quadwords, VEXPANDPS singles, and AVX512_VBMI2’s VPEXPANDB and VPEXPANDW bytes and words.

In the optimization guide

What the optimization guide says about VPEXPANDD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Vectors

• Shuffles and lane crossing: VPCOMPRESSD and VPEXPANDD replace shuffle tables, but compressing straight to memory is microcode on Zen 4 and Zen 5.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

j = 0
for i in range(VL // 32):
    if k1[i]:
        zmm1.d[i] = src2.d[j]
        j += 1
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPEXPANDD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPERMD
• VPERMI2B
• VPERMI2D
• VPERMI2PD
• VPERMI2PS
• VPERMI2Q
• VPERMI2W
• VPERMILPD
• VPERMILPS
• VPERMPD
• VPERMPS
• VPERMQ
• VPERMT2B
• VPERMT2D
• VPERMT2PD
• VPERMT2PS
• VPERMT2Q
• VPERMT2W
• VPERMW
• VPEXPANDB
• VPEXPANDQ
• VPEXPANDW
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPINSRB
• VPINSRD
• VPINSRQ
• VPINSRW
• VPLZCNTD
• VPLZCNTQ
• VPMADD52HUQ
• VPMADD52LUQ
• VPMADDUBSW
• VPMADDWD

All 686 AVX10.1 instructions