VPEXPANDQ

VPEXPANDQ takes consecutive quadwords from the low end of its source, a register or memory, and spreads them in order over the destination elements whose mask bits are set; the others keep their values or, with {z}, become zero. It is VPEXPANDD on 64-bit elements, 2, 4 or 8 of them, and that page describes the memory form, which reads only the selected count of elements, and the loops it serves. VPCOMPRESSQ is the reverse, and VEXPANDPD the same operation under a floating-point name. It came with AVX512F, and AVX512_VBMI2 added the byte and word forms, VPEXPANDB and VPEXPANDW.

Recorded on Zen 5#

• Two of eight. vpexpandq zmm0{k1}, zmm31 with mask bits 5 and 7 set put quadwords 0 and 1 of ZMM31 in elements 5 and 7 and left the other six elements of ZMM0 alone.
• Zeroing. vpexpandq ymm17{k2}{z}, ymm30 with mask bits 0 and 3 set gave quadword 0 in element 0, quadword 1 in element 3 and zero elsewhere.

In compiled code#

At -O2 with -march=x86-64-v4, GCC 14 and Clang 23 emit VPEXPANDQ for _mm512_maskz_expandloadu_epi64, straight from memory, and for _mm256_mask_expand_epi64 on YMM registers. With the constant mask FFh on a ZMM register the expansion is a copy, and both drop it.

AMD’s Zen 5 latency spreadsheet gives two macro-ops on pipes FP1 or FP2 and latencies of 2, 4 and 5 cycles for XMM, YMM and ZMM.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

j = 0
for i in range(VL // 64):
    if k1[i]:
        zmm1.q[i] = src2.q[j]
        j += 1
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPEXPANDQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPERMI2B
• VPERMI2D
• VPERMI2PD
• VPERMI2PS
• VPERMI2Q
• VPERMI2W
• VPERMILPD
• VPERMILPS
• VPERMPD
• VPERMPS
• VPERMQ
• VPERMT2B
• VPERMT2D
• VPERMT2PD
• VPERMT2PS
• VPERMT2Q
• VPERMT2W
• VPERMW
• VPEXPANDB
• VPEXPANDD
• VPEXPANDW
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPINSRB
• VPINSRD
• VPINSRQ
• VPINSRW
• VPLZCNTD
• VPLZCNTQ
• VPMADD52HUQ
• VPMADD52LUQ
• VPMADDUBSW
• VPMADDWD
• VPMAXSB

All 686 AVX10.1 instructions