VPEXPANDW

VPEXPANDW takes consecutive words from the low end of its source and places them, in order, at the destination words whose mask bits are set; the other words keep their values, or become zero with {z}. It is the word form of VPEXPANDD, whose page explains the operation and the unpacking loop around it, and came with VPEXPANDB in AVX512_VBMI2, which x86-64-v4 lacks and -march=znver5 enables. A ZMM register holds 32 words, so the mask is the low 32 bits of a mask register; from memory, only as many words are read as the mask has bits set. VPCOMPRESSW does the reverse.

Recorded on Zen 5#

• Zeroing. With mask bits 0, 1, 3, 5, 6 and 7 set, vpexpandw xmm17{k3}{z}, xmmword ptr [...] placed the first six words of memory at those words and cleared words 2 and 4.
• Merging, in place. In vpexpandw xmm5{k4}, xmm5, with mask bits 0, 2, 5, 6 and 7, words 0 to 4 of XMM5 moved to those places, while words 1, 3 and 4 kept their old values: the words came from the source as it was before the instruction.

In compiled code#

GCC 14 and Clang 23 at -O2 with -march=znver5 emit VPEXPANDW only for the intrinsics: _mm512_maskz_expandloadu_epi16(k, p) is one vpexpandw zmm0{k1}{z}, zmmword ptr [rsi], after a KMOVD of the mask in Clang. Neither vectorizes d[i] = keep[i] ? c[j++] : 0 over uint16_t arrays.

AMD’s Zen 5 latency spreadsheet gives the same rows as for VPEXPANDB: two macro-ops, each on pipe FP1 or FP2, 2, 4 and 5 cycles for the XMM, YMM and ZMM forms. It lists the word and byte forms under AVX512F, though the SDM places them in AVX512_VBMI2.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

j = 0
for i in range(VL // 16):
    if k1[i]:
        zmm1.w[i] = src2.w[j]
        j += 1
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPEXPANDW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPERMI2D
• VPERMI2PD
• VPERMI2PS
• VPERMI2Q
• VPERMI2W
• VPERMILPD
• VPERMILPS
• VPERMPD
• VPERMPS
• VPERMQ
• VPERMT2B
• VPERMT2D
• VPERMT2PD
• VPERMT2PS
• VPERMT2Q
• VPERMT2W
• VPERMW
• VPEXPANDB
• VPEXPANDD
• VPEXPANDQ
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPINSRB
• VPINSRD
• VPINSRQ
• VPINSRW
• VPLZCNTD
• VPLZCNTQ
• VPMADD52HUQ
• VPMADD52LUQ
• VPMADDUBSW
• VPMADDWD
• VPMAXSB
• VPMAXSD

All 686 AVX10.1 instructions