x86-64.net

Instruction

VPEXTRB

Copies the byte selected by an immediate from an XMM register to a general-purpose register or memory.

Extensions
Forms
4 (2 VEX, 2 EVEX)
Data
Intel XED v2026.08.23

VPEXTRB is the VEX and EVEX form of PEXTRB, whose page covers the index fixed in the immediate, the zero extension of the register result and what compilers do without SSE4.1. Since the instruction writes a general-purpose register or a byte of memory, the newer encodings change little: there is no third operand, nothing to zero in a vector register, and only a 128-bit form. VEX.L = 1, EVEX.L’L other than 0 or a vvvv field other than 1111b raises #UD, and in 64-bit mode Intel’s table ignores VEX.W, as REX.W is ignored for PEXTRB. The VEX form needs AVX; the EVEX form needs AVX512BW or AVX10.1, and adds only XMM16 to XMM31, with no mask.

On Zen 5, vpextrb edx, xmm7, 0x22 took byte 2 of XMM7, A5h, and turned RDX from 6E3B116CDC06C925h into A5h; vpextrb byte ptr [mem], xmm1, 0x7d stored byte 13, 0Ah, and {evex} vpextrb byte ptr [mem], xmm9, 0x52 byte 2, each writing that one byte only.

In compiled code

In our builds at -O2 with -march=x86-64-v3 and x86-64-v4, GCC 14 and Clang 23 read v[3] of a vector of 16 unsigned chars with one VPEXTRB, add MOVSX for a signed char, and store *p = v[9] with the memory form. Byte 20 of a ymm register takes VEXTRACTI128 first (VEXTRACTI32X4 in GCC at -v4).

For d[i*5] = s[i] + 1 over uint8_t arrays at -v3, both compilers add 1 to 32 bytes at once and store them with 32 VPEXTRBs, 16 from each half of the ymm register. At -v4 Clang keeps the 32 addresses as quadwords in vector registers too and moves each one out with VMOVQ or VPEXTRQ before its VPEXTRB.

AMD’s latency spreadsheet for Zen 5 gives VPEXTRB two macro-ops, two per cycle, on pipes FP1 or FP2 and FP4 or FP5, as for PEXTRB. Its EVEX row gives a latency of 3 cycles, while its VEX row gives none.

Forms

Every encoding of VPEXTRB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPEXTRB m8, xmm, imm8 VPEXTRB_MEMb_XMMdq_IMMbVEX.128.66.0F3A.WIG 14 /r ibAVX
VPEXTRB r32, xmm, imm8 VPEXTRB_GPR32d_XMMdq_IMMbVEX.128.66.0F3A.WIG 14 /r ibAVX
VPEXTRB r32, xmm, imm8 VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512EVEX.128.66.0F3A.WIG 14 /r ibAVX10.1 or AVX512BW
VPEXTRB m8, xmm, imm8 VPEXTRB_MEMu8_XMMu8_IMM8_AVX512EVEX.128.66.0F3A.WIG 14 /r ibAVX10.1 or AVX512BW

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelm8, xmm, imm8r32, xmm, imm8
Sandy Bridge5 / 1p153 / 1p015
Haswell, Broadwell2 / 1p52 / 1p05
Skylake, Skylake-SP2 / 1p53 / 1p05
Ice Lake2 / 0.5p153 / 1p015
Alder Lake, Sapphire Rapids19 / 0.5p154 / 1p015
Lunar Lake2 / 0.5V2 V34 / 1.5V0 V1 V2 V3
Piledriver13 / 2FPU112 / 1.5EX0 FPFMA FPU0
Zen, Zen 25 / 3FPU1 FPU22 / 2FPU1 FPU2
Zen 3, Zen 42 / 1FP45 FPSt LSU Store1 / 1FP45
Jaguar3 / 1FPU13 / 1ALU0 FPA FPU0

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Extract: byte imm8 of xmm2 goes to m8.
VPEXTRB with imm8 = 0x05With imm8 = 0x05, m8 receives byte 5 of xmm2: a5.0123467891011121314155xmm2aa5m8or r32

Example: imm8 = 0x05.

With imm8 = 0x05, m8 receives byte 5 of xmm2: a5.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

dest.write(xmm2.b[imm8 & 15])  # zero-extended in a register

Run on AMD Zen 5 (EPYC 9645): 4 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPEXTRB m8, xmm, imm8
m8explicitwrite
xmmexplicitread
imm8explicitread
VPEXTRB r32, xmm, imm8
r32explicitwrite
xmmexplicitread
imm8explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-5
EVEX forms
AVX512-E9NF

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPEXTRB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_extract_epi8 int _mm_extract_epi8(__m128i X, const int N)

VPEXTRB r32, xmm, imm8 VEX.128 -mavxwith AVX enabled

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512BW_128N

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-286 (PEXTRB/PEXTRD/PEXTRQ)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  7. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  8. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.