x86-64.net

Instruction

VPEXTRD

Copies the doubleword selected by an immediate from an XMM register to a general-purpose register or memory.

Extensions
Forms
4 (2 VEX, 2 EVEX)
Data
Intel XED v2026.08.23

VPEXTRD is the VEX and EVEX form of PEXTRD, whose page covers element 0 and MOVD, Clang’s EXTRACTPS for the same 32 bits, and stores to scattered addresses. The newer encodings write the same general-purpose register or four bytes of memory and still read only an XMM register; there is no third operand and no wider form, and VEX.L = 1 or EVEX.L’L other than 0 raises #UD. The VEX form needs AVX. The EVEX form needs AVX512DQ, not AVX512F, or AVX10.1, and adds only XMM16 to XMM31, with no mask. With W1 the same opcode is VPEXTRQ.

On Zen 5, vpextrd edx, xmm4, 0x3c took element 0, 9D908376h, and cleared bits 63:32 of RDX; {evex} vpextrd edx, xmm9, 0x19 took element 1, F4E7DACDh; and {evex} vpextrd dword ptr [mem], xmm7, 0xb4 stored element 0 and left the bytes after it alone.

In compiled code

In our builds at -O2 with -march=x86-64-v3 and x86-64-v4, GCC 14 emits VPEXTRD for v[2] of four unsigneds and Clang 23 VEXTRACTPS, in the register and the memory form, as PEXTRD’s page explains. For element 6 of eight, GCC extracts the upper half with VEXTRACTI128 at -v3, but at -v4 rotates the element down with VALIGND and copies it with VMOVD; Clang uses VEXTRACTF128 and VEXTRACTPS.

For d[i*5] = s[i] * 3 over int arrays at -v3, both compilers now vectorize, where GCC kept the loop scalar at -v2: each half of a ymm register goes out with one VMOVD and three VPEXTRDs. At -v4 Clang stores with VPSCATTERQD instead, while GCC works on a zmm register with VPEXTRD, VALIGND and VMOVD.

AMD’s latency spreadsheet for Zen 5 gives VPEXTRD two macro-ops, two per cycle, on pipes FP0 to FP3 and FP4 or FP5. Its EVEX row gives a latency of 2 cycles, while its VEX row gives none.

Forms

Every encoding of VPEXTRD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPEXTRD m32, xmm, imm8 VPEXTRD_MEMd_XMMdq_IMMbVEX.128.66.0F3A.W0 16 /r ibAVX
VPEXTRD r32, xmm, imm8 VPEXTRD_GPR32d_XMMdq_IMMbVEX.128.66.0F3A.W0 16 /r ibAVX
VPEXTRD r32, xmm, imm8 VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512EVEX.128.66.0F3A.W0 16 /r ibAVX10.1 or AVX512DQ
VPEXTRD m32, xmm, imm8 VPEXTRD_MEMu32_XMMu32_IMM8_AVX512EVEX.128.66.0F3A.W0 16 /r ibAVX10.1 or AVX512DQ

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelm32, xmm, imm8r32, xmm, imm8
Sandy Bridge5 / 1p0153 / 1p015
Haswell, Broadwell2 / 1p52 / 1p05
Skylake, Skylake-SP2 / 1p53 / 1p05
Ice Lake2 / 0.5p153 / 1p015
Alder Lake, Sapphire Rapids12 / 0.5p154 / 1p015
Lunar Lake12 / 0.5V2 V34 / 1.5V0 V1 V2 V3
Piledriver13 / 2FPU112 / 1.5EX0 FPFMA FPU0
Zen, Zen 25 / 3FPU1 FPU22 / 2FPU1 FPU2
Zen 3, Zen 42 / 1FP45 FPSt LSU Store1 / 1FP45
Jaguar3 / 1FPU13 / 1ALU0 FPA FPU0

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Extract: doubleword imm8 of xmm2 goes to m32.
VPEXTRD with imm8 = 0x02With imm8 = 0x02, m32 receives doubleword 2 of xmm2: a2.0132xmm2aa2m32or r32

Example: imm8 = 0x02.

With imm8 = 0x02, m32 receives doubleword 2 of xmm2: a2.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

dest.write(xmm2.d[imm8 & 3])  # a register: bits 63:32 cleared

Run on AMD Zen 5 (EPYC 9645): 4 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPEXTRD r/m32, xmm, imm8
r/m32explicitwrite
xmmexplicitread
imm8explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-5
EVEX forms
AVX512-E9NF

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPEXTRD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_extract_epi32 int _mm_extract_epi32(__m128i X, const int N)

VPEXTRD r32, xmm, imm8 VEX.128 -mavxwith AVX enabled

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512DQ_128N

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512DQ
CPUID.(EAX=07H,ECX=0):EBX[17] AVX512DQ

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-286 (PEXTRB/PEXTRD/PEXTRQ)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  7. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  8. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.