VPEXTRQ instruction (AVX, AVX10.1)

VPEXTRQ is the VEX and EVEX form of PEXTRQ, whose page covers element 0 and MOVQ, and how compilers reach the high half without SSE4.1. It is VPEXTRD with W1 and keeps that page’s rules: no third operand, a 128-bit form only, and the EVEX form needing AVX512DQ or AVX10.1, which adds only XMM16 to XMM31, with no mask. Only bit 0 of the immediate counts.

On Zen 5, vpextrq r14, xmm1, 0x8e, with bit 0 clear, copied the low quadword, BCAFA295887B6E61h, to R14; {evex} vpextrq r9, xmm9, 0x39, with bit 0 set, copied the high one, 5C4F4235281B0E01h; and {evex} vpextrq qword ptr [mem], xmm17, 0x46 stored the low quadword of XMM17, a register only EVEX reaches, and left the next bytes alone.

In compiled code

In our builds at -O2 with -march=x86-64-v3 and x86-64-v4, GCC 14 and Clang 23 read v[1] of two long longs with vpextrq rax, xmm0, 1 and store it with the memory form. For v[3] of four, Clang and GCC at -v3 extract the upper half with VEXTRACTI128 and take its element 1, while GCC at -v4 rotates the element down with VALIGNQ and copies it with VMOVQ.

For d[i*3] = s[i] + 7 over long long arrays at -v3, both store each half of a ymm register with a VMOVQ and a VPEXTRQ; at -v4 Clang uses VPSCATTERQQ instead. VPEXTRQ also moves addresses out of vectors: in the byte scatter of VPEXTRB, Clang at -v4 computes 32 addresses in ymm registers and takes each out with VMOVQ or VPEXTRQ.

AMD’s latency spreadsheet for Zen 5 gives VPEXTRQ two macro-ops, two per cycle, on pipes FP0 to FP3 and FP4 or FP5, as for PEXTRQ. Its EVEX row gives a latency of 2 cycles, while its VEX row gives none.

Forms

Every encoding of VPEXTRQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VPEXTRQ m64, xmm, imm8` 64-bit mode only VPEXTRQ_MEMq_XMMdq_IMMb	`VEX.128.66.0F3A.W1 16 /r ib`	AVX
`VPEXTRQ r64, xmm, imm8` 64-bit mode only VPEXTRQ_GPR64q_XMMdq_IMMb	`VEX.128.66.0F3A.W1 16 /r ib`	AVX
`VPEXTRQ r64, xmm, imm8` 64-bit mode only VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512	`EVEX.128.66.0F3A.W1 16 /r ib`	AVX10.1 or AVX512DQ
`VPEXTRQ m64, xmm, imm8` 64-bit mode only VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512	`EVEX.128.66.0F3A.W1 16 /r ib`	AVX10.1 or AVX512DQ

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`m64, xmm, imm8`	`r64, xmm, imm8`
Sandy Bridge	5 / 1p015	3 / 1p015
Haswell, Broadwell	2 / 1p5	2 / 1p05
Skylake, Skylake-SP	2 / 1p5	3 / 1p05
Ice Lake	2 / 0.5p15	3 / 1p015
Alder Lake, Sapphire Rapids	12 / 0.5p15	4 / 1p015
Lunar Lake	12 / 0.5V2 V3	4 / 1.5V0 V1 V2 V3
Piledriver	13 / 2FPU1	12 / 1.5EX0 FPFMA FPU0
Zen, Zen 2	5 / 3FPU1 FPU2	2 / 2FPU1 FPU2
Zen 3, Zen 4	2 / 1FP45 FPSt LSU Store	1 / 1FP45
Jaguar	3 / 1FPU1	3 / 1ALU0 FPA FPU0

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Extract: quadword imm8 of xmm2 goes to m64.

Example: imm8 = 0x01.

With imm8 = 0x01, m64 receives quadword 1 of xmm2: a1.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

dest.write(xmm2.q[imm8 & 1])

Run on AMD Zen 5 (EPYC 9645): 4 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VPEXTRQ r/m64, xmm, imm8` 64-bit mode only
`r/m64`	explicit	write
`xmm`	explicit	read
`imm8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms: avx-type-5
EVEX forms: AVX512-E9NF

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPEXTRQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_extract_epi64` `long long _mm_extract_epi64(__m128i X, const int N)`	`VPEXTRQ r64, xmm, imm8` VEX.128 -mavxwith AVX enabled

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX` AVX	AVX `CPUID.01H:ECX[28]` AVX	Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
`AVX512DQ_128N` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512DQ `CPUID.(EAX=07H,ECX=0):EBX[17]` AVX512DQ	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6

AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

AVX512DQ_128N

AVX10.1

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

AVX512DQ
CPUID.(EAX=07H,ECX=0):EBX[17] AVX512DQ

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

In compiled code#